It jobs in Malaysia

• Lead the development of UVM-based testbenches for both block‑level and system‑level verification.
• Define comprehensive verification plans based on design specifications and functional requirements.
• Develop reusable verification components such as drivers, monitors, scoreboards, and agents.
• Implement constrained‑random, directed, and coverage‑driven test scenarios to validate functionality.
• Analyze functional and code coverage metrics, and drive closure of coverage gaps.
• Integrate and verify third‑party IPs and interface protocols (e.g., RISC‑V, AMBA, ISP, MIPI).
• Mentor and guide junior verification engineers in UVM methodology and best practices.
• Collaborate with cross‑functional teams to review specifications, participate in design and verification reviews, and contribute to continuous process improvement.
• Document verification environments, test plans, and results for project tracking and future reuse.

• Minimum 8 years of experience in digital verification.
• Bachelor's degree or higher in Electrical Engineering or Computer Science.
• Strong proficiency in Verilog/SystemVerilog.
• Fluent in Mandarin and English.
• At least 5 years of experience leading projects or managing R&D teams.

A fabless semiconductor design firm headquartered in Asia, specializing in display driver ICs and power management ICs for applications in consumer electronics, automotive, IoT, and industrial markets. The company focuses on mixed‑signal design, offering solutions like LCD/LED drivers, timing controllers, switching regulators, and motor drivers. It is publicly listed in Taiwan and partners with global customers for innovative, low‑power display and power solutions.

• Competitive salary ranging from MYR 240,000 to MYR 420,000 annually.
• New setup / pioneering position.
• Chance to be involved in new innovative product lines.