Digital IC Verification Manager

Michael Page; Kuala Lumpur; On-site; MYR 240,000 - 420,000; Full time

Job summary

A semiconductor design firm is seeking a Senior Verification Engineer based in Kuala Lumpur. The candidate will lead UVM-based testbench development and define verification plans while mentoring junior engineers. With a strong background in digital verification and a bachelor's degree in Electrical Engineering or Computer Science, the preferred candidate should also be fluent in Mandarin and English. Competitive salary ranging from MYR 240,000 to MYR 420,000 annually is offered, along with innovative project involvement.

Benefits

Competitive salary

Innovative product lines opportunity

Qualifications

• Minimum 8 years of experience in digital verification.
• Strong proficiency in Verilog/SystemVerilog.
• At least 5 years of experience leading projects or managing R&D teams.

Responsibilities

• Lead the development of UVM-based testbenches for verification.
• Define verification plans based on design specifications.
• Develop reusable verification components.
• Implement various test scenarios to validate functionality.
• Analyze coverage metrics and close gaps.

Skills

Verilog/SystemVerilog

Leading projects

Digital verification

Mentoring junior engineers

Fluent in Mandarin

Fluent in English

Education

Bachelor's degree in Electrical Engineering or Computer Science

Job description

Responsibilities

• Lead the development of UVM-based testbenches for both block‑level and system‑level verification.
• Define comprehensive verification plans based on design specifications and functional requirements.
• Develop reusable verification components such as drivers, monitors, scoreboards, and agents.
• Implement constrained‑random, directed, and coverage‑driven test scenarios to validate functionality.
• Analyze functional and code coverage metrics, and drive closure of coverage gaps.
• Integrate and verify third‑party IPs and interface protocols (e.g., RISC‑V, AMBA, ISP, MIPI).
• Mentor and guide junior verification engineers in UVM methodology and best practices.
• Collaborate with cross‑functional teams to review specifications, participate in design and verification reviews, and contribute to continuous process improvement.
• Document verification environments, test plans, and results for project tracking and future reuse.

Qualifications

• Minimum 8 years of experience in digital verification.
• Bachelor's degree or higher in Electrical Engineering or Computer Science.
• Strong proficiency in Verilog/SystemVerilog.
• Fluent in Mandarin and English.
• At least 5 years of experience leading projects or managing R&D teams.

Company Overview

A fabless semiconductor design firm headquartered in Asia, specializing in display driver ICs and power management ICs for applications in consumer electronics, automotive, IoT, and industrial markets. The company focuses on mixed‑signal design, offering solutions like LCD/LED drivers, timing controllers, switching regulators, and motor drivers. It is publicly listed in Taiwan and partners with global customers for innovative, low‑power display and power solutions.

Compensation & Benefits

• Competitive salary ranging from MYR 240,000 to MYR 420,000 annually.
• New setup / pioneering position.
• Chance to be involved in new innovative product lines.