Design jobs in Malaysia
Place and Route Engineers- Multiple postions
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Celestica Inc.
Place and Route Engineers- Multiple postions
Job summary
A leading firm in microelectronics is seeking a Physical Design Engineer in Petaling Jaya to manage power planning, verification, and optimization. The candidate should have 3-5 years of experience, strong skills in microelectronics physical implementation, and proficiency with tools like Cadence RTL Compiler. This position offers opportunities for Malaysians and Expats, along with the requirement for occasional travel.
Qualifications
- 3-5 years of professional experience in microelectronics physical implementation.
- Good verbal and writing communication skills.
- Understanding of fabrication process variation impacts.
- Ability to work in a team environment.
Responsibilities
- Power planning, optimization, and power grid routing.
- Perform physical verification including DRC, ERC, LVS.
- Conduct post-synthesis and post-layout static timing analysis.
- Mentor new employees and implement QA/QC standards.
Skills
Tools
Work closely with front end design engineers to translate RTL-to-GDSII. Responsible for all aspects of physical design and implementation. Participate in the efforts of establishing physical design methodologies and flow automation. Work on chip and block floorplan, power/ clock distribution, chip assembly, P&R, and timing closure. Implement and monitor Quality Assurance/Quality Control standards based on corporate guidelines in a project setting. Train/mentor new employees.
- Power planning, optimization, power grid and signal routing considering timing constraints.
- Design floor planning, analogue and memory macro placement.
- Place and route including timing closure.
- Extraction of layout parasitics and SPEF/ SDF generation. Signal integrity tests.
- Post-synthesis static timing analysis (STA) and post-layout STA.
- Physical verification (DRC, ERC, LVS, ANTENNA rules).
- Writing, running, optimization of scripts for above tasks.
- Implement and monitor Quality Assurance/Quality Control standards based on corporate guidelines in a project setting.
- Have done multiple tape outs and proven record of designing complex ICs in state of the art CMOS process technologies and has successfully placed products into volume production, preferably multiple times.
- At least 3-5 years professional experience in microelectronics physical implementation.
- Good verbal and writing communication skills. Fabrication process variation impacts and performance.
- Experience in low-power design techniques.
- Good understanding of ERC, EMI rules and impact on final chip verification and cycle time reduction.
- Ability to work in a team environment and participate in cross-functional activities.
- Experience with the following tools:
- Mandatory: Cadence RTL Compiler, SOC-Encounter/ EDIS, ETS, EPS
- Desirable: Mentor Calibre/ Assura
- Malaysians and Expats are welcome to apply.
- Candidates must be willing to travel abroad.
- Candidates must be open for outsourcing to different locations apart from our primary locations (Petaling Jaya and Penang).
- Candidates must be willing to submit 3 recent paystubs while submitting resume.
* The salary benchmark is based on the target salaries of market leaders in their relevant sectors. It is intended to serve as a guide to help Premium Members assess open positions and to help in salary negotiations. The salary benchmark is not provided directly by the company, which could be significantly higher or lower.