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Lead Analog Layout Engineer (RF Integration Focus)
Job summary
A leading engineering consultancy in Penang is seeking a Senior Staff Analog Layout Engineer to lead RF layout designs. The ideal candidate will have extensive RF/analog layout experience and be skilled in layout verification. Responsibilities include guiding junior engineers and ensuring high-performance circuit delivery through collaboration and project management. Strong analytical and communication skills are essential for success in this role.
Qualifications
- 8 to 15 years of hands-on RF/analog layout experience.
- Strong knowledge in high-frequency RF blocks like LNA, Mixer, PA.
- Experience in layout verification (LVS, DRC).
Responsibilities
- Lead and execute complex RF/analog layout designs.
- Optimize circuit layouts with RF designers.
- Plan and execute RF floor planning and DRC/LVS verification.
Skills
Education
Tools
Job Openings Lead Analog Layout Engineer (RF Integration Focus)
Senior Staff Analog Layout Engineer (RF Layout) to lead and execute complex RF/analog layout designs, guide junior engineers, and collaborate cross-functionally to ensure high-performance circuit delivery.
Key Responsibilities:
- Collaborate with RF designers to optimize and iterate circuit layouts.
- Perform critical circuitblock, subsystem, and top-level layout using Cadence Virtuoso VXL & Mentor Calibre and advanced RF node processes.
- Plan and execute RF floor planning, routing, and DRC/LVS verification.
- Lead/co-lead RF IP layout and ensure design quality through reviews.
- Coordinate with cross-functional teams for layout integration.
- Conduct internal and external design reviews.
- Manage project schedules and assign tasks within the layout team.
- Mentor and coach junior engineers for quality and timely delivery.
Required Skills:
- 8 to 15 years of hands-on RF/analog layout experience (especially from scratch).
- Strong knowledge in high-frequency RF blocks (LNA, Mixer, PA, VCO, PLL).
- Deep understanding of submicron CMOS analog layout concepts.
- Skilled in parasitic reduction, matching, ESD, and DFM techniques.
- Experience in layout verification (LVS, DRC).
- Strong analytical, problem-solving, and productivity improvement focus.
- Excellent communication and team collaboration skills.
Additional Info:
- Bachelor's degree in EE/ECE/Physics with VLSI exposure preferred.
- Prior experience in WLAN/BT chip layout design is an advantage.
* The salary benchmark is based on the target salaries of market leaders in their relevant sectors. It is intended to serve as a guide to help Premium Members assess open positions and to help in salary negotiations. The salary benchmark is not provided directly by the company, which could be significantly higher or lower.