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Senior Chip Layout Engineer
Zusammenfassung
A leading recruitment agency in Malaysia is seeking a layout engineer to participate in floor planning and routing for semiconductor projects. The role involves layout verification, optimization, and collaboration with design teams. Candidates should have experience with analog devices and knowledge of various process technologies. This position is vital for ensuring high-performance circuits meet chip level standards.
Aufgaben
- Participate in sub-blocks and module-blocks floor planning and routing from scratch.
- Perform layout blocks verification with sign-off in area.
- Good hands-on experience in analog layout device matching techniques.
- Co-work with architect, design lead, designers, layout lead and layout engineers.
- Responsible for layout optimization and post layout extraction.
- Specific technical expertise in a broad range of process technologies.
- Proactively look for continuous improvement opportunities in the layout flow methodologies.
- Participate in sub-blocks and module-blocks floor planning and routing from scratch.
- Perform layout blocks verification with sign-off in area (such as DRC, LVS, ANT, ERC & PERC) and troubleshooting the results.
- Good hands-on experience in analog layout device matching techniques, high speed shielding and validation, as well to have acquired broader knowledge in handling high voltage devices.
- Co-work with architect, design lead, designers, layout lead and layout engineers to achieve modules/full chip integration, place and route, chip level verification and tape-out.
- Responsible for layout optimization, post layout extraction and parasitic analysis by ensuring analog and mixed signals circuits meet chip level tape-out, sign-off at desired area, performance, and power.
- Specific technical expertise is desired in a broad range of process technologies from Bipolar, CMOS, DMOS (BCD) to FinFET advance node in complex, high-performance analog and mixed signals circuits layout.
- Proactively look for continuous improvement opportunities in the complete layout flow methodologies (flow, layout, and design) as well as develop accurate IC layout design schedules and resource estimates.
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