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The Display IP is one of the foundational IP's within AMD and is incorporated in all AMD SOC's which feature direct connectivity to a display device through Display Port, HDMI or USB‑C connectors. Beyond the output encoding, the Display IP plays a significant role in the pixel processing and system power reduction strategies within the SOC.

The Display Controller team within the Radeon Technologies Group (RTG) is looking for an individual to participate in the design verification of the Display IP.

The candidate would participate in a team of design verification, architects and design engineers, working closely with other team members to understand and verify the functionality of the design within the context of the unit, block, and overall system. The candidate would be responsible for carefully documenting and executing test plans consisting of directed and random tests to be run under simulation and hardware acceleration and to add and collect functional coverage. Experience with hardware modelling, assertions, coverage and formal verification methods are required. The candidate would be encouraged to adopt evolving verification methodologies used in the industry as well as develop custom techniques to functionally verify increasingly complex IP designs within ambitious schedules.

• Join in the development of leading-edge display technologies and understand the architecture of the Display IP and functional blocks being designed.
• Use advanced verification methodologies for the verification of complex designs.
• Own and execute on verification of a sizable design by applying UVM verification methodology.
• Work with existing tools/flows or develop new tools/flows to complete the assigned verification task.
• Compose test and coverage plan, and validation vectors to ensure functional completeness.
• Build SystemVerilog and/or C/C++ models and test sequence libraries for simulation.
• Build test bench, agents, monitors and scoreboard for DUV.
• Debug function/performance bugs of Display IP.

• Solid understanding of ASIC IP verification methodologies and processes.
• Must be proficient in Verilog and System Verilog language.
• Must have working experience with UVM.
• Must be good at C/C++ programming, and working in Linux and Windows environments.
• Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation/emulation tools.
• Must have ASIC design verification experience in test plans, test creation, and triage, coverage and assertion, etc.
• Must be proficient in script language like Perl, Python.
• Must have excellent writing and communication skills.
• Must demonstrate strong analytical thinking and problem-solving skills with excellent attention to detail.
• Must have good teamwork and interpersonal skills.

BASc, MASc or PhD in Electrical Engineering or Computer Engineering.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.