Senior Staff Design Verification Engineer

AMD; Penang; On-site; MYR 80,000 - 120,000; Full time

Job summary

A leading semiconductor company in Malaysia is seeking an experienced engineer to join their Central Engineering Group. You will be responsible for verifying new and existing features for High Speed IO Protocol IPs such as USB, PCIe, and Ethernet. The ideal candidate will have a strong background in digital design, experience debugging firmware, and excellent communication skills to collaborate with teams across different locations. A Bachelor's or Master's in computer or electrical engineering is required.

Responsibilities

• Lead project and resolve technical issues with solutions suggested.
• Collaborate with architects and engineers to understand new features.
• Build test plan documentation for interactions with features.
• Estimate time required for new feature tests.
• Build directed and random verification tests.
• Debug test failures and work with engineers to resolve defects.
• Review functional and code coverage metrics.

Skills

IP level ASIC verification

Debugging firmware and RTL code using simulation tools

UVM testbenches

Linux environment

Windows environment

Verilog

System Verilog

C

C++

USB, UFS, Ethernet, PCIE

Power aware simulations

Perl

Ruby

Shell scripting

Education

Bachelor's or Master's degree in computer engineering/Electrical Engineering

Job description

THE ROLE:

As a member of the Central Engineering Group, you will help bring to life cutting‑edge designs.
As a member of the Central Engineering Group, you will help bring to life cutting‑edge designs. The focus of this role is to plan, build, and execute the verification of new and existing features for High Speed IO Protocol IPs (USB, PCIe, Ethernet, UFS) that is used in AMD’s product portfolio resulting in no bugs in the final design.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem‑solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBLITIES:

• Able to lead project and resolve technical issues with solutions suggested.
• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified.
• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases.
• Estimate the time required to write the new feature tests and any required changes to the test environment.
• Build the directed and random verification tests.
• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues.
• Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements.

PREFERRED EXPERIENCE:

• Proficient in IP level ASIC verification
• Proficient in debugging firmware and RTL code using simulation tools.
• Proficient in using UVM testbenches and working in Linux and Windows environments.
• Strong background with UVM, Verilog, System Verilog, C, and C++
• USB, UFS, Ethernet, PCIE, AXI knowledge is a plus
• Developing UVM based verification frameworks and testbenches, processes and flows.
• Automating workflows in a distributed compute environment.
• Exposure to power aware simulations is a plus
• Good understanding and hands‑on experience in the UVM concepts and SystemVerilog language. (SVA, UVM scoreboard)
• Good working knowledge of SystemC and TLM with some related experience.
• Scripting language experience: Perl, Ruby, Makefile, shell preferred.
• Exposure to leadership or mentorship is an asset.
• Over 11 yrs of digital IP verification with SV/UVM/formal verification or new methodology of the industry

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering.