Senior Analog Layout Engineer - Malaysian Only (REF07)

EPS Consultants Pte Ltd; Kuala Lumpur; On-site; MYR 90,000 - 120,000; Full time

Job summary

A leading engineering consultancy in Kuala Lumpur is looking for a Senior Analog Layout Engineer to take ownership of the layout design for analog and mixed-signal ICs. The ideal candidate has over 7 years of experience in IC layout and a strong command of EDA tools like Cadence Virtuoso and Calibre. This position involves leading complex layout projects, guiding junior engineers and ensuring high-quality physical implementations. The role also requires scripting knowledge for automation and a solid understanding of CMOS technologies.

Qualifications

• Bachelor’s or Master’s in Electrical Engineering, Microelectronics, or related field.
• 7+ years of experience in analog/mixed-signal IC layout.
• Strong understanding of CMOS and FinFET process technologies.

Responsibilities

• Lead the physical layout of complex analog/mixed-signal blocks.
• Run and resolve DRC, LVS, and ERC issues.
• Guide and review the work of junior layout engineers.

Skills

Layout Design Ownership

Knowledge of Cadence Virtuoso

Scripting (SKILL, Python, TCL)

Education

Bachelor’s or Master’s in Electrical Engineering

Tools

Cadence Virtuoso

Calibre

Mentor Graphics

Job description

Senior Analog Layout Engineer - Malaysian Only (REF07)

A Senior Analog Layout Engineer plays a critical role in the design and physical implementation of analog and mixed-signal integrated circuits (ICs). This position requires deep technical expertise, precision, and collaboration with cross‑functional teams. Here’s a comprehensive overview of the typical roles and responsibilities:

Core Responsibilities

• Layout Design Ownership
• Lead the physical layout of complex analog/mixed‑signal blocks (e.g., PLLs, ADCs, DACs, power management ICs)
• Perform top‑level floor planning and hierarchical layout integration
• Creating and optimizing custom analog layouts using industry‑standard EDA tools, focusing on performance, area, and power.
• Apply matching, shielding, isolation, and parasitic minimization strategies
• Optimize for performance, area, and manufacturability
• Verification & Signoff
• Run and resolve issues from DRC (Design Rule Check), LVS (Layout vs. Schematic), and ERC (Electrical Rule Check)
• Perform parasitic extraction and support post‑layout simulations
• Work closely with circuit designers, verification engineers, and process engineers
• Interpret circuit schematics and translate them into optimized physical layouts
• Guide and review the work of junior layout engineers
• Share best practices and contribute to layout methodology improvements
• Use industry‑standard EDA tools like Cadence Virtuoso, Calibre, and Mentor Graphics
• Scripting knowledge (e.g., SKILL, Python, TCL) is often expected for automation

Requirements

• Bachelor’s or Master’s in Electrical Engineering, Microelectronics, or related field
• 7+ years of experience in analog/mixed‑signal IC layout
• Strong understanding of CMOS and FinFET process technologies
• Proven track record of successful tape‑outs