IC Design Engineers (Junior / Senior / Staff)

Jobstreet Malaysia; Kedah; Hybrid; MYR 70,000 - 90,000; Full time

Job summary

A leading semiconductor design firm in Malaysia is seeking SoC / RTL / Physical Design Engineers to work on cutting-edge System-on-Chip projects. This role offers the opportunity to grow with a rapidly expanding team, focusing on next-gen implementation flows and complex digital designs. Candidates must have a strong foundation in Verilog/VHDL and digital circuit design. The company values innovation, collaboration, and technical excellence.

Benefits

Structured development guided by industry veterans

International project exposure

Job security with IPO ambitions

Qualifications

• Minimum 2 years related experience with strong foundation in digital circuit design.
• Proficient in Verilog/VHDL + exposure to verification tools.
• Knowledge of STA and timing analysis methods.

Responsibilities

• Craft high-quality RTL code that powers cutting-edge SoCs.
• Own RTL integration: coding, checkers, SDC, timing collaterals.
• Run Static Timing Analysis (STA) and ensure designs meet performance targets.

Skills

Verilog/VHDL

Digital circuit design

Static Timing Analysis (STA)

Scripting (Python, Perl)

Analytical mindset

Education

Bachelor's/Master's in Electrical or Computer Engineering

Tools

Verification tools

Job description

Overview

SoC / RTL / Physical Design Engineers
Permanent | Onsite / Remote
Multiple Openings - Junior to Senior Levels

Build the Future of Chip Design

Are you ready to take your career to the next level in physical design? Join a fast-growing semiconductor design services company that’s delivering cutting-edge System-on-Chip (SoC) projects for global clients across the consumer, automotive, and industrial sectors.

Be part of a highly collaborative team working on advanced nodes (7nm/5nm/3nm) and get hands-on exposure to complex digital designs and next-gen implementation flows.

Responsibilities

• Craft high-quality RTL code (Verilog/VHDL) that powers cutting-edge SoCs.
• Own RTL integration: coding, checkers, SDC, timing collaterals, and routing channel design.
• Run Static Timing Analysis (STA) and ensure designs meet performance targets.
• Create SDCs, perform linting & CDC checks to keep designs clean and robust.
• Integrate circuits into larger systems — making everything work seamlessly.
• Collaborate on testing & release to deliver production-ready designs.

Qualifications

• Bachelor’s/Master’s in Electrical or Computer Engineering or related courses.
• Minimum 2 years related experience with strong foundation in digital circuit design.
• Proficient in Verilog/VHDL + exposure to verification tools.
• Knowledge of STA and timing analysis methods.
• Scripting know-how (Python, Perl, etc.).
• Problem-solver with a sharp analytical mindset.
• A team player who can also work independently.

What Sets This Opportunity Apart

• Growth Trajectory: Company is scaling up with new Team of Engineers
• Projects that Matter: Work with top-tier semiconductor company
• Global Outlook: International project exposure and potential cross-country expansion.
• Mentorship & Career Path: Structured development guided by industry veterans.
• Job Security & IPO Vision: Backed by a strong pipeline and IPO ambitions within 2 years.
• Local Talent First: A strong commitment to nurturing homegrown engineering talent.

Ready to Design the Future?

Join a team that values innovation, collaboration, and technical excellence. Apply now!

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