Principal Engineer

Sinergia Talents; Kuching; On-site; MYR 200,000 - 250,000; Full time

Job summary

A leading engineering consultancy is seeking multiple Engineers for Principal, Staff, and Associate Staff roles in Kuching, Sarawak. The positions focus on semiconductor development with responsibilities including process management and yield improvement. Candidates should have at least 3 years of experience in semiconductor engineering, a relevant Bachelor's degree, and hands-on skills in various technical competencies. The role offers a competitive salary between RM 8,000.00 - 15,000.00 and is full-time.

Qualifications

• Experience in semiconductor processes with over 3 years in a related role.
• Technical expert with a proven ability to handle routine and non-routine tasks.
• Hands-on skills in wafer fab process recipe setup.

Responsibilities

• Participate in development projects to set up process recipes.
• Oversee yield improvement activities.
• Design experiments to solve production issues.

Skills

Thin Films

Wet Etching

CMOS

Stepper

Photolithography

Sputtering

Plasma-Enhanced Chemical Vapor Deposition (PECVD)

Education

Bachelor's Degree in Engineering

Master's Degree or PhD in Engineering

Job description

Engineers - Principal/ Staff/ Associate Staff

Kuching, Sarawak, Malaysia

RM 8,000.00 - 15,000.00 (Malaysian Ringgit)

About the job Engineers - Principal/ Staff/ Associate Staff

(5 positions - Module Development/Transfer Project)

Dept: Module PI Operation

• Requirement as per below technical competency
• Enclosed example of JD template for your reference

MAJOR JOB DESCRIPTION

• Participating in development project with RD Engr and to set-up unit process recipe on available tools / BKM recipe / process flow to meet development success criteria.
• Participating in continuous improvement activities (Defect improvement, Process stability)
• Oversee overall yield improvement activities with the module and YE.
• Work with process engineers on process running condition (DOE) versus tool capability.
• Able to communicate well between Module and YE / RD / QA / Etc
• Able to work with YE / RD / CP to develop COT+ / CUSP process flow

MAJOR RESPONSIBILITIES

• Process Management
• To set-up new process recipe, provide recommendation and integration guidelines to RD Engr and module PE for new development project.
• Coordinate new process or new technology evaluation/discussion between module and YE & R/D Engr.
• To identify process limitations, assess process manufacturability and process integration margin on existing tool for new development.
• Able to Pre review and define COT+ / CUSP before start evaluation.
• Capable to design the DOE to solve the in line / PCM / Sort issue

Yield Improvement

• Utilize Best Know method (BKM) recipe and process flow for the production.
• Reduce unnecessary process step for the production.
• Task Force Team (TFT) participation or involve PSM to solve or improve current production issue.
• Facilitate engineers for problem solving through DOE

POSITION REQUIREMENT

• Qualification: Bachelor Science/ Degree/ Masters / Dr in any Engineering related field
• Experience: Experience in semiconductor to enable the job holder to deal with a wide variety of problems (> 3 years)
• Skills/Competencies: The job holder will be accepted as a technical expert in his own field who is fully competent to handle both routine and non‑routine matters.
• Wafer Fab process recipe set-up experience and hands‑on skill set below for each headcount:

POSITION 1: IMPLANT TECHNICAL COMPETENCY

• Experience with AMAT VIISTAs & Purion Xe Ion Implanters preferable.
• Good knowledge with CMOS processes and unit process development experience will be added advantage

POSITION 2: DRY ETCH TECHNICAL COMPETENCY

• Experience in Silicon Oxide, Silicon Nitride, and Si/Poly‑Si etch process.
• Familiar with AMAT Centura Super‑e, AMAT Centura DPS R1 (Poly), AMAT Centura DPS+ (Poly) platform.
• Experience in SiGe etch will be a surplus.
• Experience in Silicon Nitride, Silicon oxide and Poly wet etch process and wet cleaning process
• Familiar with various wetbench tool type including dipping (DNS/Kaijo), spray (FSI) and backside film removal tool
• Experience in Furnace Deposition process, Silicon Nitride, Polysilicon and Oxidation process. Hands on skill like recipe set‑up and process tuning is important.

POSITION 4: THIN FILM HDP/PECVD TECHNICAL COMPETENCY

• Familiar and process hands on experience with Applied Material HDP CVD process / PECVD process on Producer/ Novellus for recipe set‑up and fine tuning.
• Familiar and process hands on experience with Applied Material Endura Sputtering System for PVD for recipe set‑up and fine tuning.
• Involved in continuous improvement project, process recipe optimization and development.

POSITION 5: PHOTOLITHOGRAPHY TECHNICAL COMPETENCY

• Experience with New module setup and qualification
• Hands on experience with Nikon stepper/scanner and Tel Track Act‑8. Including recipe creation, stepper job creation.
• Familiar with 0.11um technology node design rule and KrF RET

Seniority Level

Mid‑Senior level

Employment Type

Full‑time

Job Functions

(none)

Skills

• Thin Films
• Wet Etching
• CMOS
• Stepper
• Photolithography
• Sputtering
• Plasma-Enhanced Chemical Vapor Deposition (PECVD)