Senior Silicon Verification Engineer (UVM) — Hybrid, Penang

Advanced Micro Devices; Penang; Hybrid; MYR 80,000 - 120,000; Full time

Job summary

A global technology leader is seeking a Verification Engineer in Penang, Malaysia, to work within the Central Engineering Group. The role involves verifying High Speed IO Protocol IPs (USB, PCIe, Ethernet), ensuring design excellence, and collaborating with cross-functional teams. Candidates should have a strong background in digital design and verification, relevant experience in UVM and SystemVerilog, and excellent problem-solving skills. The position offers a hybrid working environment with competitive benefits.

Qualifications

• Over 7 years of digital IP verification experience with SV/UVM.
• Good understanding of UVM concepts and SystemVerilog.
• Experience in automating workflows in a distributed compute environment.

Responsibilities

• Work independently on DV tasks and provide technical guidance.
• Collaborate with architects and engineers to verify new features.
• Build test plan documentation and estimate support requirements.

Skills

IP level ASIC verification

Debugging firmware and RTL code

UVM testbenches

Verilog

System Verilog

C

C++

Scripting languages (Perl, Ruby)

Education

Bachelor's or Master's in Computer Engineering/Electrical Engineering

Tools

Simulation tools

Linux

Windows

Job description

A global technology leader is seeking a Verification Engineer in Penang, Malaysia, to work within the Central Engineering Group. The role involves verifying High Speed IO Protocol IPs (USB, PCIe, Ethernet), ensuring design excellence, and collaborating with cross-functional teams. Candidates should have a strong background in digital design and verification, relevant experience in UVM and SystemVerilog, and excellent problem-solving skills. The position offers a hybrid working environment with competitive benefits.