Design Engineer – RTL, IP Integration & Verification

Lattice Semiconductor; Penang; On-site; MYR 70,000 - 100,000; Full time

Job summary

A global semiconductor company based in Penang seeks an experienced engineer for ASIC/FPGA IP development. Candidates should be proficient in RTL design, experienced with EDA tools, and have strong communication skills. This role involves ownership of design and integration processes in a fast-paced environment, contributing to innovative projects. The candidate must thrive in a team-oriented setting.

Qualifications

• Good understanding in ASIC/FPGA IP or SoC development cycle.
• Knowledge and experience in High-Speed Serial Protocols.
• Proficient in RTL design with Verilog or System Verilog.

Responsibilities

• Own unit level design and IP integration.
• Design quality check with EDA tool and methodology exposure.
• Support silicon power-on and post silicon validation.

Skills

ASIC/FPGA IP development

High-Speed Serial Protocols

RTL design with Verilog/System Verilog

Logic simulation EDA tools (Cadence Xcelium, Synopsys VCS)

Programming (Perl, Shell Scripting, TCL, Java, Python, C/C++)

Strong communication skills

Job description

A global semiconductor company based in Penang seeks an experienced engineer for ASIC/FPGA IP development. Candidates should be proficient in RTL design, experienced with EDA tools, and have strong communication skills. This role involves ownership of design and integration processes in a fast-paced environment, contributing to innovative projects. The candidate must thrive in a team-oriented setting.