Staff IP Design Engineer - FPGA Connectivity Architect

Lattice Semiconductor; Penang; On-site; MYR 120,000 - 160,000; Full time

Job summary

A leading technology company is seeking a Staff IP Design Engineer in Penang, Malaysia. The ideal candidate will have extensive experience in high-speed SERDES protocols and FPGA RTL design, with strong programming skills in C/C++, Perl, TCL, or Python. This role offers the opportunity to work in a dynamic, team-oriented environment focused on innovation. Join us to contribute to groundbreaking connectivity solutions!

Qualifications

• 10+ years of system design experience (8 for MS, 6 for PhD).
• Independent, self-motivated, and capable in dynamic environments.
• Innovative problem solver with good communication skills.

Responsibilities

• Build Connectivity IP portfolios for Lattice FPGA.
• Translate specifications into high-speed RTL design.
• Collaborate closely with architects on design projects.

Skills

High speed SERDES protocols

FPGA RTL design

Programming (C/C++, Perl, TCL, Python)

Logic verification

Debugging and timing closure

Education

BS/MS/PhD in Electronics or Computer Engineering

Job description

A leading technology company is seeking a Staff IP Design Engineer in Penang, Malaysia. The ideal candidate will have extensive experience in high-speed SERDES protocols and FPGA RTL design, with strong programming skills in C/C++, Perl, TCL, or Python. This role offers the opportunity to work in a dynamic, team-oriented environment focused on innovation. Join us to contribute to groundbreaking connectivity solutions!