SoC Digital Design

Reeracoen Recruitment; Petaling Jaya; On-site; MYR 100,000 - 150,000; Full time

Job summary

A hiring agency in Malaysia is looking for a skilled layout designer to participate in floor planning and ensure the integration of high-performance analog circuits. The ideal candidate should have hands-on experience in layout verification, analog device matching techniques, and familiarity with high voltage devices. Responsibilities include verifying layouts, collaborating with design teams, and optimizing layouts to meet performance requirements. This role offers a chance to contribute to complex IC designs.

Qualifications

• Hands-on experience with analog layout techniques.
• Proficient in layout verification and troubleshooting.
• Familiarity with CMOS, DMOS, and FinFET process technologies.

Responsibilities

• Participate in floor planning and routing from scratch.
• Verify layout blocks with sign-off in required areas.
• Collaborate with engineers for module and chip integration.

Skills

Analog layout device matching techniques

High-speed shielding and validation

Troubleshooting verification results

Knowledge of high voltage devices

Job description

Reeracoen Recruitment – Damansara, Selangor

• Participate in sub-blocks and module-blocks floor planning and routing from scratch.
• Perform layout blocks verification with sign-off in area (such as DRC, LVS, ANT, ERC & PERC) and troubleshooting the results.
• Good hands-on experience in analog layout device matching techniques, high speed shielding and validation, as well to have acquired broader knowledge in handling high voltage devices.
• Co-work with architect, design lead, designers, layout lead and layout engineers to achieve modules/full chip integration, place and route, chip level verification and tape-out.
• Responsible for layout optimization, post layout extraction and parasitic analysis by ensuring analog and mixed signals circuits meet chip level tape-out, sign-off at desired area, performance, and power.
• Specific technical expertise is desired in a broad range of process technologies from Bipolar, CMOS, DMOS (BCD) to FinFET advance node in complex, high-performance analog and mixed signals circuits layout.
• Proactively look for continuous improvement opportunities in the complete layout flow methodologies (flow, layout, and design) as well as develop accurate IC layout design schedules and resource estimates.