Silicon Integration Design Engineer

Lattice Semiconductor; Penang; On-site; MYR 100,000 - 150,000; Full time

Job summary

A tech company specializing in programmable logic solutions is seeking a Hardware Integration Design Engineer in Malaysia, Penang. The role involves implementing chip designs, collaborating across teams, and performing design checks. Ideal candidates should have experience in hardware integration and FPGA modeling. Join a dynamic environment focused on innovation and excellence.

Qualifications

• Experience in FPGA modeling is advantageous.
• Ability to collaborate with multiple teams (architecture, verification, software).
• Knowledge of SOC integration is important.

Responsibilities

• Implement sections or full chip based on IP requirements.
• Collaborate with architecture, verification, and software teams.
• Conduct design checks and timing analysis.

Skills

Hardware Integration Design

Scripting

RTL Design

Power Estimation

Timing Analysis

Job description

Lattice Overview

There is energy here9energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Responsibilities & Skills

Detailed Description

• Hardware Integration Design Engineer is responsible for implementation of either sections or full chip, by understanding requirement of individual IPs, how they work together at system level and then SOC them all together.
• Work includes collaboration with architecture, verification and software teams.
• Responsibilities include scripting, rtl or schematic design, power and size estimates, generation of the address maps, working with packaging on pin migration, design checks and timing analysis.
• FPGA timing model and power model know-how and knowledge will be added advantage.
• Help with chip bring-up, validation, and characterization.