Senior Analog Layout Engineer - Malaysian Only (REF07)

EPS Consultants; Kuala Lumpur; On-site; MYR 100,000 - 140,000; Full time

Job summary

A leading company seeks a Senior Analog Layout Engineer to oversee the design and implementation of analog and mixed-signal ICs. This role involves collaboration with various engineering teams, utilizing advanced design techniques and tools like Cadence Virtuoso and Calibre. Ideal candidates will have substantial experience (7+ years) in IC layout with a solid educational background in Electrical Engineering. Mentorship and leadership within the team are key components of this position.

Qualifications

• 7+ years of experience in analog/mixed-signal IC layout.
• Strong understanding of CMOS and FinFET process technologies.
• Proven track record of successful tape-outs.

Responsibilities

• Lead the physical layout of complex analog/mixed-signal blocks.
• Perform top-level floor planning and verify designs with DRC/LVS/ERC.
• Guide junior layout engineers and contribute to best practices.

Skills

Layout Design Ownership

Advanced Layout Techniques

Collaboration

Education

Bachelor's or Master's in Electrical Engineering

Tools

Cadence Virtuoso

Calibre

Mentor Graphics

Job description

A Senior Analog Layout Engineer plays a critical role in the design and physical implementation of analog and mixed-signal integrated circuits (ICs). This position requires deep technical expertise, precision, and collaboration with cross-functional teams. Here's a comprehensive overview of the typical roles and responsibilities:

Core Responsibilities

• Layout Design Ownership
• Lead the physical layout of complex analog/mixed-signal blocks (e.g., PLLs, ADCs, DACs, power management ICs)
• Perform top-level floor planning and hierarchical layout integration
• Creating and optimizing custom analog layouts using industry-standard EDA tools, focusing on performance, area, and power.
• Advanced Layout Techniques
• Apply matching, shielding, isolation, and parasitic minimization strategies
• Optimize for performance, area, and manufacturability
• Verification & Signoff
• Run and resolve issues from DRC (Design Rule Check), LVS (Layout vs. Schematic), and ERC (Electrical Rule Check)
• Perform parasitic extraction and support post-layout simulations
• Collaboration
• Work closely with circuit designers, verification engineers, and process engineers
• Interpret circuit schematics and translate them into optimized physical layouts
• Mentorship & Leadership
• Guide and review the work of junior layout engineers
• Share best practices and contribute to layout methodology improvements
• Tool Proficiency
• Use industry-standard EDA tools like Cadence Virtuoso, Calibre, and Mentor Graphics
• Scripting knowledge (e.g., SKILL, Python, TCL) is often expected for automation

Typical Qualifications

• Bachelor’s or Master’s in Electrical Engineering, Microelectronics, or related field
• 7+ years of experience in analog/mixed-signal IC layout
• Strong understanding of CMOS and FinFET process technologies
• Proven track record of successful tape-outs