Integration Design Engineer

Lattice Semiconductor; Penang; On-site; MYR 70,000 - 90,000; Full time

Job summary

A global technology company in Penang is seeking a Hardware Integration Design Engineer. The role involves implementing design sections or full chips and requires collaboration with architecture, verification, and software teams. Candidates should have experience in hardware integration design and knowledge of scripting and RTL design. This position offers an opportunity to thrive in a fast-paced, collaborative environment.

Qualifications

• Experience in hardware integration design.
• Knowledge of scripting, RTL design, and timing analysis.
• Ability to collaborate with cross-functional teams.

Responsibilities

• Responsible for the implementation of chip sections or full chip.
• Collaborate with architecture, verification, and software teams.
• Assist with chip bring-up, validation, and characterization.

Job description

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Responsibilities & Skills

Detailed Description

• Hardware Integration Design Engineer is responsible for implementation of either sections or full chip, by understanding requirement of individual IPs, how they work together at system level and then SOC them all together.
• Work includes collaboration with architecture, verification and software teams.
• Responsibilities include scripting, rtl or schematic design, power and size estimates, generation of the address maps, working with packaging on pin migration, design checks and timing analysis.
• Help with chip bring-up, validation, and characterization.