Design Eng 2

Lattice Semiconductor; Penang; On-site; MYR 60,000 - 90,000; Full time

Job summary

A leading semiconductor company is seeking a passionate digital design engineer to develop a High Speed Serial Protocol Hard-IP portfolio. You will work closely with principal engineers to translate specifications into RTL design, while optimizing for performance. Ideal candidates will have a strong background in protocols such as Ethernet, PCIe, and proficiency in Verilog or SystemVerilog. Join a dynamic team and contribute to innovative projects that are shaping the future of programmable technology.

Qualifications

• Understanding of ASIC/FPGA IP or SoC development cycles.
• Knowledge of High-Speed Serial Protocols.
• Experience in Lint, CDC, and similar methodologies.

Responsibilities

• Own unit-level design and IP integration.
• Develop design documentation and automate design flows.
• Support silicon power-on and post-silicon validation.

Skills

RTL design

Verilog

SystemVerilog

RTL verification methodologies

High-Speed Serial Protocols

Scripting

Logic simulation

Job description

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast-paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Responsibilities & Skills

We are looking for a passionate digital design engineer to build a High Speed Serial Protocol Hard-IP portfolio for Lattice FPGA. The individual should have the ability to work closely with Principal Engineers or Architects to translate specifications into RTL design, optimizing for performance, low power, and logic utilization.

Accountabilities/Exposure:

• Own unit-level design and IP integration.
• Perform design quality checks using industry-standard EDA tools and methodologies.
• Define and achieve timing constraints and convergence.
• Plan open-box tests, develop assertion checks, and debug.
• Analyze code coverage and work towards closure.
• Support silicon power-on and post-silicon validation.
• Develop new design methodologies.
• Automate design flows with scripting for daily tasks.
• Create design documentation, including micro-architecture and implementation details.

Qualifications:

• Understanding of ASIC/FPGA IP or SoC development cycles.
• Knowledge of High-Speed Serial Protocols such as Ethernet, PCIe, MIPI, or Universal Transceivers.
• Proficiency in RTL design with Verilog or SystemVerilog and constraints.
• Experience with design quality check methodologies like Lint, CDC, RDC, Fishtail, or UPF flows.
• Advanced skills in logic simulation tools such as Cadence Xcelium, Synopsys VCS, or Siemens Questa.
• Experience collaborating with Design Verification teams on test plans, assertion coding, and coverage analysis.
• Familiarity with Physical Design processes like Synthesis, LEC, or Timing Closure.
• Programming skills in Perl, Shell Scripting, TCL, Java, Python, or C/C++, and familiarity with Linux OS.
• Experience in technical writing, including micro-architecture documentation, publications, or patents.
• Self-motivated with strong communication skills, promoting innovation and teamwork.
• Experience in silicon power-on or hardware validation is a plus.