Chip Layout Project Lead

Reeracoen Recruitment; Petaling Jaya; On-site; MYR 150,000 - 200,000; Full time

Job summary

A leading recruitment firm in Malaysia is seeking a highly skilled engineer with over 7 years of experience in chip layout. The role involves participating in floor planning, verifying layouts, and optimizing designs for high-performance analog and mixed-signal circuits. Candidates must hold a degree in Electrical or Electronic Engineering with excellent problem-solving, communication, and teamwork skills. Fluency in Mandarin and English is preferred. This position offers a challenging opportunity to work on advanced technologies and lead project teams.

Qualifications

• Minimum of 7 years of experience in chip layout.
• Experience managing and guiding others.
• Strong problem-solving and analytical skills.

Responsibilities

• Participate in floor planning and routing.
• Perform layout blocks verification.
• Co-work with architects and layout engineers.
• Responsible for layout optimization and analysis.

Skills

Problem-solving skills

Analytical skills

Teamwork

Communication

Education

Bachelor's or Master's in Electrical/Electronic Engineering

Job description

Reeracoen Recruitment – Damansara, Selangor

Manufacturing(Electronics/Semiconductors)

Job Description

• Participate in sub-blocks and module-blocks floor planning and routing from scratch.
• Perform layout blocks verification with sign-off in area (such as DRC, LVS, ANT, ERC & PERC) and troubleshooting the results.
• Good hands‑on experience in analog layout device matching techniques, high speed shielding and validation, as well to have acquired broader knowledge in handling high voltage devices.
• Co‑work with architect, design lead, designers, layout lead and layout engineers to achieve modules/full chip integration, place and route, chip level verification and tape‑out.
• Responsible for layout optimization, post layout extraction and parasitic analysis by ensuring analog and mixed signals circuits meet chip level tape‑out, sign‑off at desired area, performance, and power.
• Specific technical expertise is desired in a broad range of process technologies from Bipolar, CMOS, DMOS (BCD) to FinFET advance node in complex, high‑performance analog and mixed signals circuits layout.
• Proactively look for continuous improvement opportunities in the complete layout flow methodologies (flow, layout, and design) as well as develop accurate IC layout design schedules and resource estimates.

Qualifications

• Requirement
  • Bachelor's or Master's degree in Electrical / Electronic Engineering or related field (CGPA 3.50 & above).
  • Minimum 7 years of experience in chip layout.
  • Candidate with full process of chip layout.
  • Have managerial and guiding experience.
  • Strong problem‑solving and analytical skills.
  • Good communication and teamwork skills.
• English Level -
• Other Language
  • Mandarin, English