Senior Design Engineer

Randstad; Penang; On-site; MYR 245,000 - 328,000; Full time

Job summary

A leading technology staffing firm is seeking a skilled engineer to lead junior engineers in project delivery. The role requires strong expertise in integrated analog circuit design and experience with Cadence and Synopsys for layout design. You will work on analog IC layout while ensuring high-quality delivery. The ideal candidate should possess a Bachelor's degree in a relevant field, have at least 5-7 years of design experience, and demonstrate excellent communication skills in English. Flexibility and a willingness to relocate are essential.

Qualifications

• Thorough understanding of integrated analog circuit design.
• Experience in analog IC/mixed signals IC layout designs and verifications.
• Must have good verbal and written communication skills in English.

Responsibilities

• Lead junior engineer towards projects delivery and resolve technical issues.
• Utilize EDA tools for layout design and verification.
• Attend relevant project meetings and assess timescale risks.

Skills

Integrated analog circuit design

Chip layout techniques

Experience in analog IC layout designs

Communication skills

Self-motivation

Knowledge of CMOS devices

Education

Bachelor’s degree in engineering electrical/Electronic, Physics, Computer or related fields

Tools

Cadence

Synopsys

Job description

Work and lead junior engineer towards projects delivery with other layout and circuit design engineers to resolve any technical issues that will affect layout to ensure high quality.

Utilize EDA tools (Cadence and Synopsys) for layout design and all related verification items, perform all layout activities as cell and block level creation, edit and full verification.

Use state-of-the-art layout techniques for matching, ESD, latch-up prevention and parasitic reduction and work with an awareness and understanding of the process from physical point of view.

Attending all relevant project meetings, continuous assessment and reporting of timescale risks.

Where possible, use schematic driven layout and consider top level auto routing.

Involve in review session and prepare all related document and data preparation for wafer tape out.

Additional Skills/Experience

• Thorough understanding of integrated analog circuit design
• Thorough understanding of chip layout in cell and block level creation, edit and full verification.
• Experience with layout techniques for matching, ESD, latch-up prevention and parasitic reduction and work with an awareness and understanding of the process from physical point of view.
• Experience in analog IC/ mixed signals IC layout designs and verifications. Able to perform with ideas on chip size reduction.
• Highly self-motivated and adaptable.
• Having the basic knowledge of CMOS related devices including high voltage and the skill of deciphering Design Manual.

Qualification

• Bachelor’s degree in engineering electrical/Electronic, Physics, Computer or related fields
• Must have good verbal and written communication skills in English
• Japanese is a plus

Additional Requirements

• Layout & EDA tool skill: At least 1 year of design experience as product sub leader
• Layout & EDA tool skill: Expertise with Cadence and Synopsys
• Willing to put extra effort to keep the project schedule
• At least have a minimum of 5-7 years’ experience in Analog IC layout design.
• Willing to work flexible hours to support different time zone teams
• Willing to relocate to Malaysia or other country to support Design Team.
• Must have good verbal and written communication skills in English.
• Good interpersonal, communication, and collaboration skills