Principal Silicon Design Engineer

Advanced Micro Devices; Penang; On-site; MYR 200,000 - 300,000; Full time

Job summary

A global technology company in Penang is seeking a CAD Manager to lead its CAD infrastructure team and optimize the EDA environment. Responsibilities include managing tool deployments, developing methodologies, and establishing standard design flows for multiple semiconductor projects. The ideal candidate will have over ten years of EDA experience, strong leadership, and excellent communication skills. This role offers the chance to shape technical directions and enhance design quality.

Benefits

AMD benefits at a glance

Qualifications

• 10+ years of silicon EDA and/or digital ASIC design experience.
• Experience with PPA Power Performance Area Optimization.
• Familiarity with physical aspects of VLSI designs.

Responsibilities

• Lead and manage the CAD infrastructure team supporting multiple IC design projects.
• Establish and maintain standardized design flows and methodologies.
• Implement and support customized CAD flows for Fabric design groups.
• Develop tool flow methodologies on digital back‑end domains.

Skills

Leadership

Communication

Scripting (TCL, Python)

EDA Tools Knowledge

Education

Bachelors or Masters degree in Computer Engineering/Electrical Engineering

Tools

Virtuoso based custom Layout tools

Calibre

Design Compiler

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career.

The role:

As CAD Manager you will be responsible for leading and optimizing the EDA environment for the Project CAD team in the Adaptive & Embedded Computing Group (AECG). You will oversee the complete SCH-to‑GDS flow, manage tool deployments, and drive methodology development across multiple semiconductor projects. This is an opportunity to shape the technical direction of critical IC design workflows and lead a team of skilled CAD engineers. You will advise on tools selection, and interface with various EDA tool vendors and foundries to run the EDA tools, PDKs and other files necessary for the Silicon Development Team to operate efficiently. You will be responsible for defining and creating a unified environment that sets the versions of the tools, PDK and design for every individual chip in development. Additionally, you will interact with the various Silicon development teams who will be requesting newer versions of the tools, and raise trouble tickets with CAD vendors as needed.

The person:

The ideal candidate has experience leading others in technical and managerial settings. You also have excellent communication, writing, and presentation skills.

Key Responsibilities:

• Lead and manage the CAD infrastructure team supporting multiple IC design projects
• Establish and maintain standardized design flows and methodologies
• Implement and support customized CAD flows for Fabric design groups
• Enable the team in meeting the design and development targets by working closely with external tool vendors
• Develop tool flow methodologies on digital back‑end domains, sign‑off flows for timing, power, EM/IR, DRC/LVS/DFM, etc.
• Improve engineering efficiency while improving design quality in IP release process
• Be single point contact for bugs and issues for custom and analog physical design team
• Build flow in TCL, Python to ensure quality and faster executions
• Understand different methodologies used across industry to adopt best practices
• Leverage and deploy AMD AI systems to design teams

Preferred Experience:

• 10+ years of silicon EDA and/or digital ASIC design experience
• PPA Power Performance Area Optimization
• Virtuoso based custom Layout tools and flows
• Calibre extraction flows, Totem & Redhawk for EM/IR
• TCL, Python, PERL, or other scripting languages
• 2+ years in one or more of these tools: Design compiler, IC Compiler, Fusion Compiler, Cadence Virtuoso and Custom Compiler
• Physical aspect of VLSI designs
• Strong written and verbal communication skills.

Academic Credentials:

• Bachelors or Masters degree in Computer Engineering/Electrical Engineering.

Location:

Penang, Malaysia

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.