Library Characterization Engineer

Sinergia Talents; Kuching; On-site; MYR 70,000 - 90,000; Full time

Job summary

A leading technology firm in Kuching, Malaysia is seeking a Library Characterization Engineer responsible for characterizing standard cell and custom cell libraries. The role involves developing best-in-class production flows, supporting quality library deliverables, and working closely with a globally distributed team. Ideal candidates will have a Bachelor's degree in Electronics Engineering, 2+ years of digital design experience, and strong skills in communication and teamwork. This position offers a dynamic environment focused on performance and efficiency in automotive applications.

Qualifications

• Minimum 2 years of experience in digital design activities.
• Experience in library characterization with SPICE or similar tools.
• Understanding of digital standard cells and circuits.

Responsibilities

• Develop library characterization production flow for advanced customer requirements.
• Ensure high quality library deliverables.
• Support digital library team and advanced circuit design.

Skills

TCL

Perl

Python

Shell scripting

Communication skills in English

Teamwork and collaboration

Education

Bachelors Degree in Electronics Engineering

Tools

Liberate

Primetime

Tempus

SPICE

Job description

About the job Library Characterization Engineer

We are currently looking for a Library Characterization Engineer responsible for the characterization of standard cell and custom cell libraries and generation of the latest library formats with cutting edge tools and methodologies. You will be part to the team developing state-of-the-art digital libraries allowing best-PPA digital design mainly dedicated for automotive market.

Your Role:

• Develop best-in-class library characterization production flow to meet advanced customers requirement. Responsible for timing and power characterization and generation of standard cell EDA views by implementing and maintaining cell characterization tools and flows for the most advanced silicon modeling methodologies.
• Support the First Time Right of IC Designs by ensuring high quality library deliverables. Support liberty model accuracy validation. Develop automatic QA flow including EM/IR and design checks.
• Work closely with the digital library team and support advanced circuit design and modeling, pushing the boundary of what is possible in power, performance, and area.
• Explore innovative modeling techniques for comprehending variation, layout-dependent effects, aging, simultaneous switching, etc.
• Release of digital libraries on our customers portal following standards.
• Work in an international and globally distributed team of experts.
• Customer support for Static Timing Analysis and Signoff condition recommendations.

Your Profile:

• Bachelors Degree or higher in Electronics Engineering.
• Minimum 2 years of working experience in digital design activity, ideally in library characterization with spice, internal tools, or commercial tools such as Liberate and static timing analysis with Primetime or Tempus.
• Good communication skills good level in English, written and spoken.
• Teamwork and collaboration skills, working within multinational, multisite team.
• Open, curious in new design implementation, integrity and friendly when engaging internal/external customers.
• Self‑motivated, progressive attitude, and able to work independently with minimum supervision.
• Understanding of digital standard cells, digital circuits & optimization for best-PPA.
• Understanding of Timing/Power characterization & modeling of Standard cell circuits. Knowledge of industry standard hardware design CAD software and required standard cell design view generation and validation.
• Ideally, in-depth understanding of Liberty format (NLDM, CCS, CCSN) and transistor level spice simulation. Hands‑on experience running SPICE simulations and high sigma variation analysis.
• Knowledge of static timing, power, EMIR analysis using EDA tools.
• TCL, Perl, Python, and/or Shell scripting skills are a plus.
• Good layout design knowledge & parasitic optimization in various types of layouts.