Senior Design Engineer

Renesas Electronics; Bayan Lepas; Hybrid; MYR 80,000 - 100,000; Full time

Job summary

A leading semiconductor solutions provider in Penang, Malaysia is seeking an experienced engineer to lead circuit design projects. The ideal candidate will have a bachelor's degree, excellent communication skills, and a minimum of 5-7 years' experience in Analog IC layout design. Proficiency in using Cadence and Synopsys tools is essential. This role offers a hybrid work model allowing remote work two days a week and aims to foster teamwork and collaboration in the office on designated days.

Benefits

Hybrid work model

Collaboration and continuous learning environment

Qualifications

• Minimum of 5-7 years of experience in Analog IC layout design.
• Willing to work flexible hours to support different time zone teams.
• Good interpersonal and collaboration skills.

Responsibilities

• Lead junior engineers in project delivery and resolve technical issues.
• Utilize EDA tools for layout design and verification.
• Involve in review sessions and prepare relevant documentation.

Skills

Integrated analog circuit design

Chip layout creation and verification

Layout techniques for matching and ESD

Analog IC / mixed signals IC layout design

Good verbal and written communication skills in English

Expertise in Cadence and Synopsys

Education

Bachelor’s degree in engineering electrical/Electronic, Physics, Computer or related fields

Tools

Cadence

Synopsys

Job description

Job Description

Renesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.

With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’

Main Responsibilities

• Work and lead junior engineer towards projects delivery with other layout and circuit design engineers to resolve any technical issues that will affect layout to ensure high quality.
• Utilize EDA tools (Cadence and Synopsys) for layout design and all related verification items, perform all layout activities as cell and block level creation, edit and full verification.
• Use state-of-the-art layout techniques for matching, ESD, latch-up prevention and parasitic reduction and work with an awareness and understanding of the process from physical point of view.
• Attending all relevant project meetings, continuous assessment and reporting of timescale risks.
• Where possible, use schematic driven layout and consider top level auto routing.
• Involve in review session and prepare all related document and data preparation for wafer tape out.

Skills / Experience

• Thorough understanding of integrated analog circuit design
• Thorough understanding of chip layout in cell and block level creation, edit and full verification.
• Experience with layout techniques for matching, ESD, latch‑up prevention and parasitic reduction and work with an awareness and understanding of the process from physical point of view.
• Experience in analog IC / mixed signals IC layout designs and verifications. Able to perform with ideas on chip size reduction.
• Highly self‑motivated and adaptable.
• Having the basic knowledge of CMOS related devices including high voltage and the skill of deciphering Design Manual.

Qualifications

Must Have’s

• Bachelor’s degree in engineering electrical/Electronic, Physics, Computer or related fields
• Must have good verbal and written communication skills in English
• Japanese is a plus

Supplementary Requirements

• Layout & EDA tool skill: At least 1 year of design experience as product sub leader
• Layout & EDA tool skill: Expertise with Cadence and Synopsys
• Willing to put extra effort to keep the project schedule
• At least have a minimum of 5-7 years’ experience in Analog IC layout design.
• Willing to work flexible hours to support different time zone teams
• Willing to relocate to Malaysia or other country to support Design Team.
• Must have good verbal and written communication skills in English.
• Good interpersonal, communication, and collaboration skills
• Need to work onsite

Nice To Have’s

• Proven custom layout work on blocks like: ADC/DAC, LDO, Bandgap, PMIC
• EM/IR awareness and hands‑on PWR/GND optimization
• Familiarity with sensitive Analog layout techniques (shielding, matching, guard‑ring strategy, substrate noise control)
• Strong Cadence Virtuoso expert‑level usage
• Ability to write SKILL / Python / TCL scripts to automate layout checks or flows
• Familiarity with Calibre or equivalent physical verification flows
• Good cross‑team communication with circuits, and process teams
• Strong debugging mindset when facing parasitic or mismatch issues

Additional Information

Are you ready to own your success and make your mark?
Join Renesas. Let’s Shape the Future together.

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

We have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in‑office days are Tuesday through Thursday for innovation, collaboration and continuous learning.