IP Engineering Director

Reeracoen Recruitment; Bayan Lepas; On-site; MYR 250,000 - 300,000; Full time

Job summary

A leading semiconductor company in Penang is seeking an IP Engineering Director to lead the development and delivery of reusable semiconductor IP solutions. The ideal candidate will have deep expertise in semiconductor design and proven leadership in managing engineering teams. Responsibilities include defining technical roadmaps, overseeing verification processes, and collaborating with cross-functional teams to meet performance targets. This role offers the opportunity to drive innovation in semiconductor technology.

Qualifications

• Deep expertise in semiconductor IP design, verification, and integration.
• Proven leadership in building and managing engineering teams.
• Experience in driving design methodology and automation.

Responsibilities

• Define and execute the company’s IP engineering roadmap.
• Build and lead a world-class IP engineering team.
• Lead architecture, micro-architecture, and RTL design of reusable IP.
• Oversee verification and ensure robust delivery.
• Own IP program planning, milestones, and risk management.

Skills

Semiconductor IP design

IP verification

Leadership

Collaboration

Continuous improvement

Job description

Overview

Highly skilled and visionary IP Engineering Director, to lead the development and delivery of reusable semiconductor IP that powers advanced SoCs, chiplets, and multi-die solutions. This role requires deep expertise in semiconductor IP design, verification, and integration, combined with proven leadership in building and managing engineering teams. While the position is primarily focused on hardware IP development (digital, analog, or mixed-signal), software development experience—such as firmware, device drivers, or modeling frameworks—is a strong plus, enabling HW/SW co-design, system-level optimization, and accelerated customer adoption. The IP Engineering Director will define technical roadmaps, oversee execution, and collaborate with cross-functional teams to deliver silicon-proven IP solutions that meet aggressive power, performance, and area (PPA) targets.

Responsibilities

1. Leadership & Strategy
   • Define and execute the company’s IP engineering roadmap aligned with product strategy.
   • Build and lead a world-class IP engineering team across design, verification, validation, and integration.
   • Mentor and develop engineering leaders, fostering innovation, collaboration, and technical excellence.
   • Drive continuous improvement in design methodology, automation, and productivity.
2. IP Development & Execution
   • Lead architecture, micro-architecture, and RTL design of reusable IP (e.g., memory interfaces, high-speed I/Os, interconnects, SerDes, or accelerators).
   • Oversee verification, validation, and sign-off, ensuring robust, silicon-proven IP delivery.
   • Collaborate with SoC, package, and system teams for seamless integration into chiplet and multi-die systems.
   • Support post-silicon debug, bring-up, and customer deployment of IP blocks.
3. Cross-Functional Collaboration
   • Partner with software teams on firmware, drivers, and simulation frameworks to ensure full-stack enablement.
   • Engage with product, SoC, and system architects to align IP functionality with end-market requirements.
   • Collaborate with foundries, EDA vendors, and ecosystem partners to enhance IP design flows and deployment.
4. Program Management & Delivery
   • Own IP program planning, milestones, schedules, and risk management.
   • Ensure timely delivery of high-quality IP to internal design teams and external customers.
   • Drive design reuse and scalability across multiple projects and product lines.
5. Execution & Delivery
   • Own NoC project planning, execution, and delivery, ensuring schedule adherence and quality.
   • Establish and improve design methodologies, verification flows, and automation for rapid, reliable development.
   • Support bring-up, debug, and performance validation in both pre-silicon and post-silicon environments.