Engineer- Digital Physical Design

Krisvconsulting Services Pte Ltd; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

A leading consulting firm in Penang, Malaysia is seeking an experienced Engineer specializing in Digital Physical Design. The ideal candidate will have 12+ years of expertise in RTL-to-GDS implementation, strong proficiency with EDA tools, and a robust background in team leadership. Responsibilities include leading the design flow, collaborating with global teams, and driving physical implementations. This role is critical for organizational growth and team development.

Qualifications

• Minimum of 12 years' experience in RTL-to-GDS digital physical design and implementation.
• Deep hands-on experience with industry-standard EDA tools.
• Excellent problem-solving, organizational, and communication skills in a multi-cultural environment.

Responsibilities

• Lead all aspects of RTL2GDS digital physical implementation.
• Collaborate with internal teams across functions and global sites.
• Drive floor planning, power planning, placement, routing, and timing closure.

Skills

Hands-on expertise in sub-micron ASIC implementation

Strong scripting skills in TCL, PERL, or Python

Expertise in static timing analysis

Leadership capability

Education

Bachelor's or Master's degree in Electronics Engineering or related discipline

Tools

Synopsys tools (Fusion Compiler, ICC2, PrimeTime, Design Compiler)

Cadence tools (Innovus, Tempus, Genus)

Job description

About the job Engineer- Digital Physical Design

The ideal candidate will have strong hands-on expertise in sub-micron ASIC implementation, full RTL-to-GDS flow, and a solid grasp of industry EDA tools and scripting for automation.

Responsibilities:

Lead all aspects of RTL2GDS digital physical implementation at block or full-chip level.

Collaborate with internal teams across functions and global sites to ensure timely delivery with high-quality standards.

Drive floor planning, power planning, placement, clock tree synthesis, routing, and timing closure.

Own the full design flow from constraints development through signoff and tape-out.

Perform hands-on optimization, layout verification, and design signoff using industry-standard tools.

Develop and maintain automation scripts (TCL, PERL, Python) to improve flow QoR and reduce TAT.

Provide technical guidance, problem-solving expertise, and mentorship to junior engineers.

Build and manage a high-performing physical design team as part of organizational growth.

Requirements:

Bachelors or Masters degree in Electronics Engineering or a related discipline.

Minimum of 12 years' experience in RTL2GDS digital physical design and implementation.

Deep hands-on experience with Synopsys tools (Fusion Compiler, ICC2, PrimeTime, Design Compiler).

Familiarity with Cadence tools (Innovus, Tempus, Genus) is a strong advantage.

Strong scripting skills in TCL, PERL, or Python for flow development and automation.

Proven expertise in static timing analysis, low power implementation, and physical verification.

Excellent problem-solving, organizational, and communication skills in a multi-cultural environment.

Strong leadership capability with the initiative and drive to build and lead a high-performing team.