Analog Design Project Lead

Reeracoen Recruitment; Petaling Jaya; On-site; MYR 150,000 - 200,000; Full time

Job summary

A recruitment agency in Petaling Jaya is seeking a layout design engineer to participate in floor planning and routing from scratch. The role includes verifying layout blocks, collaborating with architects and engineers, and optimizing layouts for mixed signal circuits. Key skills include experience with analog layout techniques, handling high voltage devices, and a strong understanding of complex circuit designs. This position offers a dynamic environment for continuous improvement in IC layout methodologies.

Qualifications

• Strong hands-on experience in analog layout and validation.
• Good understanding of high voltage devices.
• Ability to work in a collaborative environment with various roles.

Responsibilities

• Participate in module and sub-block floor planning and routing.
• Perform layout blocks verification and troubleshoot results.
• Collaborate with teams for module and chip integration.

Skills

Analog layout device matching techniques

High speed shielding

High voltage devices handling

Layout optimization

Parasitic analysis

Job description

Reeracoen Recruitment – Damansara, Selangor

• Participate in sub-blocks and module-blocks floor planning and routing from scratch.
• Perform layout blocks verification with sign-off in area (such as DRC, LVS, ANT, ERC & PERC) and troubleshooting the results.
• Good hands‑on experience in analog layout device matching techniques, high speed shielding and validation, as well to have acquired broader knowledge in handling high voltage devices.
• Co‑work with architect, design lead, designers, layout lead and layout engineers to achieve modules/full chip integration, place and route, chip level verification and tape‑out.
• Responsible for layout optimization, post layout extraction and parasitic analysis by ensuring analog and mixed signals circuits meet chip level tape‑out, sign‑off at desired area, performance, and power.
• Specific technical expertise is desired in a broad range of process technologies from Bipolar, CMOS, DMOS (BCD) to FinFET advance node in complex, high‑performance analog and mixed signals circuits layout.
• Proactively look for continuous improvement opportunities in the complete layout flow methodologies (flow, layout, and design) as well as develop accurate IC layout design schedules and resource estimates.