Senior Physical Design Engineer

UST Global; Penang; On-site; MYR 200,000 - 250,000; Full time

Job summary

A leading technology company based in Penang is seeking a Physical Design Engineer specialized in full-custom analog and mixed-signal layout. Responsibilities include overseeing the design and verification process, implementing cutting-edge SoC designs, and collaborating in a dynamic team environment. Candidates should have extensive experience with EDA tools such as Cadence and Synopsys, as well as a solid understanding of timing concepts and floor planning. This role offers an opportunity to work with advanced semiconductor technologies in a stimulating engineering environment.

Qualifications

• Experienced in major EDA tools including Cadence, Synopsys, and Mentor.
• Expertise in floor planning including power grid design.
• Experience in Tcl/Perl/Shell/Python programming.

Responsibilities

• Responsible for Physical design and verification.
• Implement multimillion gate SoC designs in cutting edge process technologies.
• Good understanding of timing concepts and ECO generation.

Skills

Synthesis

Place & Route

Timing Closure

Physical Verification

Python Programming

Tools

Cadence

Synopsys

Mentor Tools

Job description

Responsible for all aspects of Physical design (Place & Route, STA analysis, PI/SI analysis, physical verification, DFR design and verification, DFM design and verification, physical design data delivery.), Full custom and its implementation in a team environment performing full-custom analog and mixed-signal layout of next generation high-speed interfaces and signal integrity systems (aka SerDes, PHY) in deep submicron FinFET technologies.

Job Requirements

• Experienced in synthesis, Place & Route, timing closure, PV, PI, PPA improvement. etc and major EDA tools including Cadence, Synopsys, and Mentor tools.
• Implementation of multimillion gate SoC designs in cutting edge process technologies (16nm,14nm & below). Experience in Finfet technologies is a must.
• Expertise in floor planning including power grid design to meet EMIR specifications.
• Good understanding of timing concepts, Experience in Generating and Implementing ECOs to fix timing, noise, and EMIR violations.
• Experience in Tcl/Perl/Shell/Python programming, Mentor Calibre DRC/LVS/PERC, and Apache Totem EM & IR analysis is a plus.
• Familiar with mixed signal layout matching techniques, such as interdigitation, common centroid and dummies for matching, bypass capacitor design and optimization, power supply bus construction using star connections, critical route shielding, triple well layout, ESD device and cell layout, and guard ring layout methods.
• Knowledge of low-power UPF flows. Ability to create LEF and DEF of analog/custom blocks, define the pins ports for the block, integrate them into the P&R database, and maintain the hierarchy for extraction and verification. Need to be able to merge and integrate the database into the Cadence Virtuoso database.
• Good understanding of advanced semiconductor technology process and device physics. Strong in digital logic design, CMOS & strong analytical ability.
• Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment