Job Search and Career Advice Platform

Enable job alerts via email!

Senior Silicon Verification Engineer — IP/UVM Expert

Advanced Micro Devices

Penang

On-site

MYR 100,000 - 130,000

Full time

Today
Be an early applicant

Generate a tailored resume in minutes

Land an interview and earn more. Learn more

Job summary

A leading semiconductor company in Penang is seeking a Digital IP Verification Engineer to collaborate with cross-functional teams in verifying cutting-edge features. Candidates must possess a strong background in digital design and verification, with over 5 years of experience. Key responsibilities include building test plans, debugging failures, and ensuring design excellence in a collaborative environment. A Bachelor's or Master's degree in a related field is required, as well as proficiency in tools like UVM and Verilog.

Benefits

Comprehensive benefits package
Inclusive workplace culture

Qualifications

  • Passion for modern, complex processor architecture and digital design.
  • Experience collaborating with engineers in different timezones.
  • Over 5 years of digital IP verification experience.

Responsibilities

  • Work within a cross-functional team to plan and execute feature verifications.
  • Collaborate with hardware and firmware engineers to understand new features.
  • Build test plan documentation and estimate required time for tests.
  • Debug test failures and work to resolve design defects.
  • Modify tests based on functional and code coverage metrics.

Skills

Digital design
Analytical skills
Problem-solving skills
Communication skills

Education

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering

Tools

UVM testbenches
Verilog
System Verilog
C
C++
Linux
Windows
Job description
A leading semiconductor company in Penang is seeking a Digital IP Verification Engineer to collaborate with cross-functional teams in verifying cutting-edge features. Candidates must possess a strong background in digital design and verification, with over 5 years of experience. Key responsibilities include building test plans, debugging failures, and ensuring design excellence in a collaborative environment. A Bachelor's or Master's degree in a related field is required, as well as proficiency in tools like UVM and Verilog.
Get your free, confidential resume review.
or drag and drop a PDF, DOC, DOCX, ODT, or PAGES file up to 5MB.