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MSDV Engineer
Job summary
A technology company in the United Kingdom is seeking a Mixed Signal Design Verification Engineer. Responsibilities include implementing System Verilog models for analog blocks, verifying models against schematics, and working within UVM environments. The role requires understanding of AMS simulations and running regressions using VManager. Competitive compensation and opportunities for professional growth are offered.
Responsibilities
- Implementation of System Verilog Models for the Analog blocks.
- Model vs Schematic Verification with System Verilog Test bench.
- Understanding of adding connect module in AMS simulations.
- Understanding of UVM environment and top-level test cases.
- Running regressions using VManager.
Mixed Signal Design Verification Engineer
Responsibilities include:
- Implementation of System Verilog Models for the Analog blocks
- Model vs Schematic Verification – System Verilog Test bench implementation including assertions
- Understanding of adding connect module at the interaction of schematic and model while running AMS simulations
- Understanding of UVM environment and implementing the Top Level Test cases in the environment
- Running regressions using VManager
Principal Analog AMS RF Recruitment Specialist
* The salary benchmark is based on the target salaries of market leaders in their relevant sectors. It is intended to serve as a guide to help Premium Members assess open positions and to help in salary negotiations. The salary benchmark is not provided directly by the company, which could be significantly higher or lower.