MSDV Engineer

Chipright; United Kingdom; Remote; GBP 45,000 - 70,000; Full time

Job summary

A technology company in the United Kingdom is seeking a Mixed Signal Design Verification Engineer. Responsibilities include implementing System Verilog models for analog blocks, verifying models against schematics, and working within UVM environments. The role requires understanding of AMS simulations and running regressions using VManager. Competitive compensation and opportunities for professional growth are offered.

Responsibilities

• Implementation of System Verilog Models for the Analog blocks.
• Model vs Schematic Verification with System Verilog Test bench.
• Understanding of adding connect module in AMS simulations.
• Understanding of UVM environment and top-level test cases.
• Running regressions using VManager.

Job description

Mixed Signal Design Verification Engineer

Responsibilities include:

• Implementation of System Verilog Models for the Analog blocks
• Model vs Schematic Verification – System Verilog Test bench implementation including assertions
• Understanding of adding connect module at the interaction of schematic and model while running AMS simulations
• Understanding of UVM environment and implementing the Top Level Test cases in the environment
• Running regressions using VManager

Principal Analog AMS RF Recruitment Specialist