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[CONTRACT] UVM Verification Engineer
Résumé du poste
A technology consulting firm is seeking a UVM Verification Engineer to work on ASIC projects for an initial 6-month contract, with the option for remote work. The ideal candidate will have a strong background in ASIC verification and experience in System Verilog and UVM. Candidates with knowledge of wireless communications like WiFi or 5G will be preferred.
Qualifications
- Strong background in ASIC Verification required.
- Experience in System Verilog and UVM necessary.
- Familiarity with multi-clock domains and IP block level verification is expected.
Responsabilités
- Join a newly formed team for ASIC projects.
- Expand on existing projects while initiating new ones.
Connaissances
A client based in France is looking for a UVM verification Engineer, this will be for an initial 6 month contract with extensions. The role can be performed remotely but any on‑site would be welcomed.
The successful Verification engineer will be joining a team that is being newly formed within our client's offices and will help to expand on projects being worked, both new and existing within other teams. You will be involved in new and existing ASIC projects.
Skills :
- Strong background in ASIC Verification
- System Verilog / UVM
- Knowledge of IP block level verification
- Multi‑clock domains
- RTL within Verilog, VHDL and / or SystemVerilog
- Used to working with complex ASIC and / or large FPGA designs
- Knowledge of wireless communications such as WiFi or 5G would be good
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