NoC Verification Engineer (UVM, Python)

Qualcomm; Guyancourt; Sur place; EUR 50 000 - 70 000; Plein temps

Résumé du poste

A leading technology firm in Guyancourt seeks an ASIC Design Verification Engineer to join the NoC Verification Tool team. This role involves verifying NoC-level features, maintaining verification benches using UVM and Python, and developing automated verification regressions. Candidates should possess a Master’s or Bachelor's degree in Science or Engineering and have 2 years of relevant experience. This position offers an opportunity to work at the intersection of software and hardware verification.

Qualifications

• Master's degree in Science or Engineering field is required.
• 2+ years of experience in hardware design/verification preferred.
• Experience with UVM components or VIPs is desirable.

Responsabilités

• Verify NoC-level features.
• Develop and maintain UVM benches and required software.
• Extend automated verification regressions.

Connaissances

UVM components

Debugging skills

Object-oriented programming

Formation

Master's degree in Science or Engineering

Bachelor's degree in Science or Engineering

Outils

Verilog

Python

SystemVerilog

Linux

Git

Description du poste

A leading technology firm in Guyancourt seeks an ASIC Design Verification Engineer to join the NoC Verification Tool team. This role involves verifying NoC-level features, maintaining verification benches using UVM and Python, and developing automated verification regressions. Candidates should possess a Master’s or Bachelor's degree in Science or Engineering and have 2 years of relevant experience. This position offers an opportunity to work at the intersection of software and hardware verification.