Lead Staff Engineer - DRAM Layout & Verification

Micron Technology; Jalisco; Presencial; MXN 1,280,000 - 1,647,000; Jornada completa

Descripción de la vacante

A leader in memory solutions seeks a Layout Design Engineer in Mexico, Jalisco. This role involves designing high-density memory chips and collaborating with innovative teams on advanced DRAM products. The ideal candidate will have strong CMOS circuit knowledge and over 5 years of layout design experience. Responsibilities include layout implementation and evaluating designs, ensuring adherence to high-performance standards. This position offers a chance to work in a dynamic environment with a focus on pioneering memory technology.

Formación

• 5+ years in layout design experience.
• Strong fundamentals in high-performance techniques addressing electromigration.
• Experience with layout implementation and evaluation at chip/block level.

Responsabilidades

• Design high-density memory chips with advanced functionality.
• Lead engineers to ensure high-quality product delivery.
• Collaborate with cross-functional teams to solve layout challenges.

Conocimientos

CMOS circuit design knowledge

Debugging and problem-solving

Cadence Virtuoso Suite skills

Leadership experience

Effective communication

Educación

BS/MS in Electrical or Computer Engineering

Herramientas

LVS/DRC tools

Descripción del empleo

A leader in memory solutions seeks a Layout Design Engineer in Mexico, Jalisco. This role involves designing high-density memory chips and collaborating with innovative teams on advanced DRAM products. The ideal candidate will have strong CMOS circuit knowledge and over 5 years of layout design experience. Responsibilities include layout implementation and evaluating designs, ensuring adherence to high-performance standards. This position offers a chance to work in a dynamic environment with a focus on pioneering memory technology.