Digital IC Verification Engineer

ic resources; Parma; In loco; EUR 40.000 - 70.000; Tempo pieno

Descrizione del lavoro

A leading company in power electronics is looking for a UVM Verification Engineer to join their expanding team in Parma. The role involves developing test plans, performing verification at multiple levels, and collaborating closely with designers. Candidates should have strong knowledge of HDL and scripting languages, with preferred experience in UVM environments and EDA tools.

Competenze

• Experience with HDL for testbenches creation.
• Knowledge in scripting languages like Tcl and Python.
• Understanding of ASIC design flow and verification.

Mansioni

• Develop test plans, tests, and verification infrastructure using SV / UVM.
• Perform block-level and system-level verification.
• Build reusable bus functional models and monitors.

Conoscenze

HDL (SystemVerilog / Verilog / VHDL)

Scripting languages (Tcl, Python)

ASIC design flow knowledge

UVM environments knowledge

EDA vendors simulators experience

Silicon validation experience

Git experience

Descrizione del lavoro

Working for a leader in power in power electronics, this is a great opportunity to join a growing team, as UVM verification engineer.

Job duties :

• Developing test plans, tests and verification infrastructure using SV / UVM methodology
• Building reusable bus functional models, monitors, checkers and scoreboards
• Performing block level, multi-block level and system-level verification
• Performing Mixed Signal simulations
• Implementing Regression tests
• Working closely with IC designers and post-silicon engineers

Qualifications and Background

Requirements :

• Knowledge / experience with HDL (SystemVerilog / Verilog / VHDL), particularly for testbenches creation
• Knowledge / experience in scripting languages, such as Tcl and Python
• Some knowledge of ASIC design flow and related verification step

Nice to have :

• Knowledge of UVM environments and classes
• Some experience with main EDA vendors simulators such as Questasim and Xcelium
• Knowledge of DFT structures and test pattern generation
• Some experience in silicon validation / characterisation
• Experience working on Git.

For more information, please contact Rob Hudson.

Digital Engineer • Parma, Emilia Romagna