Digital Verification Engineer

microTECH Global Ltd; Les Clayes; Sur place; EUR 60 000 - 80 000; Plein temps

Résumé du poste

A leading technology company is looking for a Digital Verification Engineer for their projects in France. This role involves verifying complex ASIC designs for high-performance servers using UVM methodologies and requires skills in SystemVerilog and C++. The ideal candidate is proficient in developing test plans and debugging simulation errors, ensuring high-quality verification.

Qualifications

• Proven success in verifying complex SoC / ASIC and IP.
• Experience with Constraint-Random / Coverage-Driven verification environments.

Responsabilités

• Acquire knowledge of ASIC architecture through specifications.
• Draft verification specs and test plans with the logic design team.
• Develop verification environments using UVM-SystemVerilog / C++.
• Monitor, analyze, and debug simulation errors.
• Optimize tests to meet coverage objectives.

Connaissances

UVM verification methodology

Constraint-Random verification

SystemVerilog / C++ proficiency

Problem-solving skills

Outils

Simulation and coverage monitoring tools

Description du poste

Overview

Job Title : Digital Verification Engineer

Job Type : Permanent

Location : Sophia Antipolis OR Les Clayes-sous-Bois FRANCE

Start : ASAP

My client is a next-generation digital business, it holds worldwide prominence in digital, cloud, data, advanced computing, and security. With a presence in more than 47 countries and a team of 55, world-class talents, the company leverages high-end technologies across the digital continuum to expand the possibilities of data and technology for current and future generations.

Mission Overview

In the realm of ASIC development, specifically for network controllers, routers, cache coherence controllers, and processors tailored for high-end, high-performance Bull servers (catering to "big data" and "exascale" servers), the mission entails active participation in the verification process of a complex ASIC. This involves utilizing the Constraint-Random, Coverage Driven functional verification methodologies, which form the foundation of the UVM verification standard.

Primary Responsibilities

• Acquire in-depth knowledge of ASIC architecture and microarchitecture through the study of specifications and collaborative interactions with architecture and logic design teams.
• Draft verification specifications and collaborate closely with the logic design team to formulate comprehensive test plans.
• Develop verification environments using UVM-SystemVerilog / C++, including tests and coverage models.
• Monitor, analyze, and debug simulation errors to ensure the integrity of the verification process.
• Analyze coverage results from simulations, optimizing tests to meet coverage objectives within specified deadlines.

Key Skills

• Proven success in verifying complex SoC / ASIC and IP.
• Proficiency in UVM verification methodology.
• Experience in creating Constraint-Random / Coverage-Driven verification environments in SystemVerilog / C++ covering drivers / monitors, constrained random tests, self-verifying checkers, and coverage models in SystemVerilog-Covergroup / SVA, along with mastery of object-oriented programming.
• Familiarity with simulation and coverage monitoring tools.
• Efficient problem-solving, including quick identification of root causes and development of fixes or workarounds.