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Mixed Signal Design Verification Engineer
Zusammenfassung
A leading engineering firm in the UK is seeking a Mixed Signal Design Verification Engineer. The role involves implementing System Verilog models, performing verification tasks, and understanding AMS simulations. Experience with UVM environments is essential. This position offers a very attractive salary.
Qualifikationen
- Experience in implementing System Verilog Models for Analog blocks.
- Proficient in Model vs Schematic Verification.
- Understanding of UVM environment and Top Level Test cases.
Aufgaben
- Implement System Verilog Models for Analog blocks.
- Verify Models against Schematics with Test bench implementation.
- Run AMS simulations and regressions.
Kenntnisse
Salary: Very Attractive Rate
Location: N/A
Mixed Signal Design Verification Engineer
- Implementation of System Verilog Models for the Analog blocks
- Model vs Schematic Verification – System Verilog Test bench implementation including assertions
- Understanding of adding connect module at the interaction of schematic and model while running AMS simulations
- Understanding of UVM environment and implementing the Top Level Test cases in the environment
- Running regressions using VManager
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