Python jobs in United States
Turbomachinery Mechanical Design Engineer
Pangea Aerospace
Discover more opportunities than anywhere else. Find more jobs now
Connect with headhunters to apply for similar jobsSupport Technician (Ref Support Technician 2025-08 CB)
ICIQ
Data Analyst & BI Engineer con experiencia en Cloud
Centro Tecnológico del Notariado
Logistics Handling Operations Administrator Ontigola
American President Lines
Senior Product Data Analyst — Remote, Data-Driven Impact
EcoVadis
Instructor de Data & Analytics — Formación Intensiva
thePower
Senior Systems Test Engineer - SoC & Embedded Automation
MaxLinear, Inc.
Senior LLM Scientist - Quantum-AI Research Leader (Hybrid)
Hyperproof
Senior AI Engineer — Enterprise LLM & ML Pipelines
Frontiers
Senior Digital Design Engineer
Job summary
A technology company in Madrid is seeking a PCIe Lead / Senior Digital Design Engineer to design and integrate PCIe solutions in complex SoC / ASIC environments. Candidates should have over 4 years of experience, strong skills in PCIe design, and proficiency in RTL design. This permanent role offers the opportunity to work with cross-functional teams in a dynamic setting.
Qualifications
- 4+ years industrial experience for Engineer, 6+ years for Lead.
- Strong hands-on experience with PCIe.
- Solid background in SoC / ASIC IP integration.
Responsibilities
- Own the architecture and lead the RTL implementation of PCIe subsystems.
- Drive efficient interaction between PCIe block and CPU clusters using AMBA-CHI coherency.
- Integrate and verify IPs within large SoC environments.
Skills
Education
PCIe Lead / Senior Digital Design Engineer
Barcelona, Spain
Negotiable
Permanent
We’re looking for an experienced engineer to take a leading role in the design and integration of PCIe solutions within complex SoC / ASIC environments. If you’re passionate about microprocessor architecture, high-speed I / O, and building high-performance subsystems, this role puts you at the centre of it.
- Own the architecture and lead the RTL implementation of PCIe subsystems
- Drive efficient interaction between the PCIe block and CPU clusters using AMBA-CHI coherency
- Integrate and verify IPs within large SoC environments
- Work closely with cross-functional teams of digital, verification, and architecture experts
- 4+ years industrial experience (Engineer) or 6+ years (Lead)
- Strong hands-on experience with PCIe (design and / or integration)
- Solid background in SoC / ASIC IP integration
- Proficiency in RTL design (Verilog or VHDL)
- Experience with basic block-level testing
- Familiarity with at least one protocol : AXI, CHI, or AHB
- Master’s degree or PhD
- Knowledge of C++, Python, Perl, Bash, or TCL
- Experience working with version control (git, svn)
- Understanding of coherency protocols
- Experience with CXL
- Exposure to common digital design tools (Synthesis, STA, CDC, Lint, etc.)
* The salary benchmark is based on the target salaries of market leaders in their relevant sectors. It is intended to serve as a guide to help Premium Members assess open positions and to help in salary negotiations. The salary benchmark is not provided directly by the company, which could be significantly higher or lower.