ASIC VERIFICATION ENGINEER

High Tech Genesis Inc.; Ottawa; On-site; CAD 70,000 - 90,000; Full time

Job summary

A leading design services company in Ottawa is seeking a Verification Engineer to push technological boundaries. The ideal candidate has experience in System Verilog, UVM, and programming skills in C and Python. You will develop verification plans, create testbenches, and collaborate with systems engineers. This position offers a dynamic work environment within a diverse team committed to innovation.

Qualifications

• Experience in using System Verilog.
• Experience in using UVM.
• Experience in programming languages: C and Python.
• Must have excellent problem-solving skills.

Responsibilities

• Read and understand architecture and requirements.
• Validate architectural functional blocks using various methods.
• Develop test plans and create testbench environments.
• Perform coverage-driven verification and debug failures.
• Provide regular updates on verification progress.

Skills

System Verilog

UVM

C

Python

Problem-solving

Job description

Overview

WE'RE HIRING! At HTG, you’ll push boundaries with the latest tech and collaborate with a team that loves what they do. Be part of a design services company that is amongst the companies that lead the world in technology and innovation.

Your next chapter starts here.

Responsibilities

• Read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects.
• Thoroughly validate one or more architectural functional blocks using a combination of simulation, formal, and coverage methods.
• Develop verification, functional coverage and formal verification test plans.
• Create testbench environments and components, agents, scoreboard, and test scenarios using System Verilog UVM and/or C.
• Perform coverage-driven verification, monitor regressions, and debug failures with the support of the function's designer.
• Provide regular status updates on verification progress on a regular basis.

Qualifications

• Experience in using System Verilog
• Experience in using: UVM
• Experience in using programming languages: C and Python
• Must have an excellent problem solver

High Tech Genesis Inc. is an Equal Opportunity Employer. Diversity and inclusion are at the core of our values.

Please advise High Tech Genesis of any accommodation measures you may require.

Application information

1. Applicants must have the legal right to work in Canada.
2. Please submit your resume in Microsoft Word format when applying for this position.