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Engineer jobs in United States

Design Verification Engineer (SOC/ASIC/Verilog)

Design Verification Engineer (SOC/ASIC/Verilog)
HKM HR MANAGEMENT PTE. LTD.
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SGD 65,000 - 100,000
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Experience ATM Expert / Applied Researcher

Experience ATM Expert / Applied Researcher
Borr Drilling
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Electrical Project Engineer

Electrical Project Engineer
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Senior Data Engineer
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Quantitative Developer

Quantitative Developer
P2P
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(Sr./Staff) Software Engineer, Edge AI - Toolchain

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IT Support Engineer

IT Support Engineer
Pathlight School / Autism Resource Centre (Singapore)
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Principal/Senior Control & Instrumentation Engineer

Principal/Senior Control & Instrumentation Engineer
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Singapore
SGD 80,000 - 100,000

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Information Technology - Cloud/DevOps Engineer
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RECRUIT EXPRESS PTE LTD
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SGD 60,000 - 80,000

(Sr./Staff) Algorithm Engineer - Image Processing

(Sr./Staff) Algorithm Engineer - Image Processing
OMNIVISION TECHNOLOGIES SINGAPORE PTE. LTD.
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Manufacturing Engineer (Project Based)

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APPLIED MATERIALS SOUTH EAST ASIA PTE. LTD.
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SGD 40,000 - 70,000

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IT Support Engineer
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Senior / Engineer (Environmental)

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SGD 70,000 - 100,000

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AI Engineer
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IT & Network Engineer
Borr Drilling
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SGD 50,000 - 80,000

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Borr Drilling
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SGD 40,000 - 60,000

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SGD 60,000 - 90,000

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Design Verification Engineer (SOC/ASIC/Verilog)

HKM HR MANAGEMENT PTE. LTD.
Singapore
SGD 65,000 - 100,000
Job description

Responsibilities:

  • Work closely with design engineers and architects to create and document detailed test plans for verifying the SoC design.
  • Establish and manage the infrastructure and environment for automated verification of the SoC's architecture, functionality, and performance.
  • Develop reusable testbenches, test cases using constrained-random and directed methods, and verification modules for both block and system levels.
  • Create a regression strategy, methodology, and scripting tools, ensuring comprehensive function coverage and addressing verification gaps before design releases and tape-out.
  • Collaborate with design engineers to troubleshoot and resolve simulation issues.
  • Provide support to test engineers during post-silicon validation.
  • Mentor and guide team members and junior engineers, aiming to enhance verification efficiency.

Requirements:

  • Master in Electrical Engineering or equivalent with 8 years of relevant working experience/ PhD in Electrical Engineering or equivalent with 3 years working experience.
  • Extensive understanding of UVM/OVM, Semiformal Verification, assertion-based verification, and hardware-software co-verification methodology.
  • Skilled in Verilog, SystemVerilog, Python, Perl, TCL, Shell scripting, C/C++, SystemC, and assembly coding for industry-standard ISAs.
  • Familiar with MIPI, AMBA (APB/AHB/AXI) bus protocols, RISC-V/ARM, or DSP cores.
  • Experience in verifying designs at RTL and post-P&R gate levels.

__________________________________________________________

HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact win@hkmsvs.com for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628

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* The salary benchmark is based on the target salaries of market leaders in their relevant sectors. It is intended to serve as a guide to help Premium Members assess open positions and to help in salary negotiations. The salary benchmark is not provided directly by the company, which could be significantly higher or lower.

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