Memory Mask Layout Design Engineer

North American Production Sharing de México, S.A. de C.V.; Tijuana; Presencial; MXN 441,000 - 618,000; Jornada completa

Descripción de la vacante

A leading semiconductor company in Tijuana seeks a motivated SRAM Mask Layout Designer for an entry-level role. The position offers a chance to work on cutting-edge technologies and focuses on physical layout design for SRAM and memory circuits. Candidates should have an Associate's degree in a related field and possess a strong attention to detail and teamwork skills. Preferred qualifications include familiarity with CMOS technology and scripting languages, making this a perfect opportunity for recent graduates eager to grow in the semiconductor industry.

Formación

• Associate’s degree or Certificate in relevant field.
• Basic understanding of CMOS technology and IC design principles.
• Strong attention to detail and ability to work in a team.

Responsabilidades

• Assist in creating physical layouts for SRAM.
• Perform layout verification including DRC, LVS, and ERC.
• Collaborate with circuit designers to ensure layout meets requirements.
• Maintain layout database utilizing Design Management software.
• Engage with design team to understand concepts and constraints.
• Proactively solve design and PDK issues.

Conocimientos

Attention to detail

Teamwork

Communication

Educación

Associate's degree in Computer Science, Mathematics, Electrical Engineering

Bachelor's degree in Computer Science, Engineering

Herramientas

Cadence Virtuoso

SKILL

Python

Descripción del empleo

We are looking for a highly motivated SRAM Mask Layout Designer to join our custom memory design team. This entry-level position offers an opportunity to work on cutting‑edge semiconductor technologies and gain hands‑on experience in physical layout design for SRAM and other memory circuits.

Job description

• Assist in creating physical layouts for SRAM and custom memory blocks using industry‑standard CAD tools (e.g., Cadence Virtuoso).
• Perform layout verification including DRC (Design Rule Check), LVS (Layout vs. Schematic), and ERC.
• Collaborate with circuit designers to ensure layout meets performance, reliability, and manufacturability requirements.
• Maintain layout database utilizing Design Management software.
• Engage with the engineering design team to understand design concepts, constraints, and milestones. Concisely and accurately report design status to the layout and engineering team; track schedules.
• Proactively and independently solve design and PDK issues; clearly communicate solutions to the layout and engineering team.
• Work closely with circuit Designers/ Mask Layout Designers across global sites (such as the U.S., Taiwan and India)
• Demonstrate effective communication and teamwork, work efficiently as part of an international team.

Minimum Qualifications

• Associate’s degree/Certificate in computer Science, Mathematics, Electrical Engineering or related field
• Basic understanding of CMOS technology and IC design principles.
• Strong attention to detail and ability to work in a team environment.

Preferred Qualifications

• Bachelor’s degree in computer science, Engineering, or related field.
• Understanding of parasitic effects and reliability considerations.
• Familiarity with scripting languages (SKILL, Python) for layout automation.
• Knowledge of advanced process nodes (e.g., FinFET, GAA) is a plus.