Mixed-Signal Verification Engineer (SystemVerilog/UVM)

Apple; Livorno; In loco; EUR 50.000 - 70.000; Tempo pieno

Descrizione del lavoro

A leading technology company is seeking an experienced engineer to join their Analog Mixed Signal Design Verification Team. The role involves developing verification test plans, designing test benches, and collaborating with various teams to ensure compliance with system requirements. Candidates should have a Master’s in Electrical Engineering and hands-on experience with mixed signal verification tools. This position is full-time based in Livorno, Italy.

Competenze

• Hands-on experience in mixed signal verification using EDA tools.
• Experience in behavioral modelling targeting analog, digital or mixed signal verification environments.
• Teammate with excellent written and verbal communication skills.

Mansioni

• Work within the Analog Mixed Signal Design Verification Team to achieve top-level mixed signal verification.
• Develop comprehensive verification test plans.
• Design and implement test benches and tools to verify target performance.

Conoscenze

Mixed signal verification

Analog and digital design background

Behavioral modelling using System Verilog

Knowledge of UVM and Assertion-Based Verification

Scripting languages (Python / Perl / TCL)

AI and ML understanding

Communication skills

Formazione

Masters in Electrical Engineering or equivalent

Descrizione del lavoro

A leading technology company is seeking an experienced engineer to join their Analog Mixed Signal Design Verification Team. The role involves developing verification test plans, designing test benches, and collaborating with various teams to ensure compliance with system requirements. Candidates should have a Master’s in Electrical Engineering and hands-on experience with mixed signal verification tools. This position is full-time based in Livorno, Italy.