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Digital Design Verification Engineers (x2)
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Digital Design Verification Engineers (x2)
Job summary
A leading tech company in the United Kingdom is looking for Digital Design Verification Engineers to focus on design verification of integrated circuits. Candidates should have a Master’s degree in Electrical / Computer Engineering and at least 3 years of relevant experience, or a Bachelor’s with 5 years experience. Strong skills in System Verilog and UVM are essential. The role involves responsibility for test benches, automated simulations, and leading the design verification team.
Qualifications
- 3+ years of experience in Design Verification or 5 years with leadership experience.
- Strong proficiency in System Verilog and UVM.
- Ability to work under high pressure and mentor team members.
Responsibilities
- Responsible for design verification of integrated circuits.
- Creation of test benches and automated verification simulations.
- Performing block level and top level design verification.
Skills
Education
Tools
Salary: Very Attractive Rate
Location: N/A
Your tasks and responsibilities
- Responsible for design verification of integrated circuits, using both directed tests and constrained random regressions
- Primary focus is on digital design verification, but proficiency with mixed signal design verification and creation / validation of models are strong advantages
- Proficiency in System Verilog and UVM, including: writing checkers and assertions, customizing constraints, getting functional coverage collection using cover groups, etc.
- Technical and team leadership – both within the internal project DV team, but also directly supporting demanding customers.
- Creation of test benches and automated verification simulations
- Performing block level and top level design verification
- Generation of relevant documentation (DV Plan, DV execution plan, customer reviews, etc.)
- Master’s degree in Electrical / Computer Engineering with 3 years of experience in Design Verification, or a Bachelor’s degree with 5 years of experience including at least 3 years in team or technology leadership role
- System Verilog / UVM based DV experience
- Collaborative and respectful team player with mentoring skills, and passionate about the team’s success
- Excellent communication skills (both oral and written) are required, as customer level technical interface and design / team leadership is necessary sometimes under high pressure situations.
- Experience with relevant CAD tools
* The salary benchmark is based on the target salaries of market leaders in their relevant sectors. It is intended to serve as a guide to help Premium Members assess open positions and to help in salary negotiations. The salary benchmark is not provided directly by the company, which could be significantly higher or lower.