Senior Debug & Trace Hardware Architect

SiFive; La Ciotat; Sur place; EUR 193 000 - 237 000; Plein temps

Résumé du poste

A leading technology firm in La Ciotat is seeking a Hardware Design Technical Lead passionate about designing advanced debug, trace, and profiling solutions. This role focuses on enhancing RISC-V processors for a dynamic market and demands a strong background in RTL design. The ideal candidate will have over 7 years of experience in hardware architecture and a relevant master's or PhD. Join us at the forefront of innovation, where your contributions can make a significant impact.

Prestations

Competitive salary

Comprehensive benefits package

Incentive compensation

Qualifications

• 7+ years of industry experience leading architecture and RTL design for debug/trace/profiling hardware.
• Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL.
• Knowledgeable in debug interfaces, JTAG, cJTAG.

Responsabilités

• Architect, design and implement debug, trace and profiling hardware.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework.
• Work with architecture, performance, software and hardware teams.

Connaissances

Debugging tools

CPU architectures

Team collaboration

Attention to detail

Formation

MS/PhD in Electrical Engineering, Computer Engineering, Computer Science or a related technical discipline

Outils

Verilog

System Verilog

VHDL

Chisel/Scala

Description du poste

A leading technology firm in La Ciotat is seeking a Hardware Design Technical Lead passionate about designing advanced debug, trace, and profiling solutions. This role focuses on enhancing RISC-V processors for a dynamic market and demands a strong background in RTL design. The ideal candidate will have over 7 years of experience in hardware architecture and a relevant master's or PhD. Join us at the forefront of innovation, where your contributions can make a significant impact.