Principal System Design Architect

Arm Limited; Biot; Hybride; EUR 80 000 - 110 000; Plein temps

Résumé du poste

A leading technology company in France is seeking a Principal System Design Architect to drive the architecture and RTL implementation of sophisticated digital subsystems. The ideal candidate will have expert-level knowledge in digital design and RTL, experience leading design reviews, and confirmed ownership of major design blocks. This position offers competitive compensation, flexible working arrangements, and the opportunity to shape design decisions in a collaborative environment.

Prestations

Competitive compensation

Flexible working

Collaborative engineering culture

Qualifications

• Expert-level knowledge in digital design and RTL.
• Experience leading design reviews and technical direction.
• Confirmed ownership of at least one major design block end-to-end.

Responsabilités

• Lead the architecture and RTL implementation of digital subsystems.
• Produce high-quality design documentation and mentor engineers.
• Drive SoC-level integration readiness and make independent design trade-offs.

Connaissances

Digital design & RTL

SystemVerilog / Verilog

FSMs and control logic

Pipelines and latency management

CDC mechanisms

Scripting (Python / Tcl / Bash)

Formation

Degree in Electrical Engineering, Computer Engineering, or equivalent

Outils

Cadence simulator

Synopsys simulator

Siemens simulator

Description du poste

About the role

We are looking for a Principal System Design Architect to take technical ownership of a major digital subsystem within a sophisticated SoC.

This role is for asenior digital designerwho leads architecture and RTL implementation, makes independent design decisions, and sets the technical bar for correctness, scalability, and robustness.

You willlead a defined technical area, influence design direction beyond your immediate team, and deliver solutions that materially impact product quality and programme success.

Missions

• Be responsible for themicro-architecture and RTL designof a sophisticated digital subsystem or IP.
• Translate system requirements intoclean, scalable RTL architectures.
• Leadmulti-clock domaindesign:
• CDC architecture and partitioning
• Clock gating and clock-enable strategy
• Robust reset synchronisation
• Leadmulti-power domaindigital design
• Power-state aware RTL
• Isolation, retention, and reset interactions
• Power sequencing considerations
• DriveSoC-level integration readiness, including:
• Interface definition and ownership
• Clock, reset, and power integration
• Performance and latency trade-offs
• Make and defendindependent design trade-offs
• Producehigh-quality design documentation
• Lead and influencedesign reviews, challenging weak designs and raising overall design quality.
• Mentor engineers onsophisticated digital design techniques.
• Collaborate with verification, physical design, and validation teams to ensure design intent is correctly realised

Technical Skills

Digital design & RTL

• Expert-levelSystemVerilog / Verilogfor synthesizable RTL.
• Confirmed experience designinglarge, sophisticated RTL blocksthat are:
• Readable and maintainable
• Parameterised and reusable
• Scalable across projects
• Strong command of:
• FSMs and control logic
• Pipelines and latency management
• Arbitration and flow control
• Error handling and recovery

Clocking & reset

• Deep experience withmulti-clock domain systems:
• CDC mechanisms (async FIFO, handshakes, synchronisers)
• Clock domain partitioning
• Robust reset architecture design:
• Global vs local reset strategy
• Safe bring-up and recovery

Power-aware design

• Experience designingmulti-power domaindigital logic.
• Strong understanding of how power intent affects RTL structure and behaviour.
• UPF awareness (authoring not required).

SoC & system awareness

• Good understanding of SoC fundamentals:
• Interconnects (AMBA)
• Addressing and memory-mapped control
• Performance bottlenecks and contention
• Ability to reason beyond local RTL into system-level impact.

Design leadership

• Experience leading design reviews and technical direction.
• Recognised as atechnical authorityin digital design.
• Comfortable owning decisions that affect a significant part of the product.

Design-for-verification (expected, not primary)

• Strong design-for-verification
• Clean interfaces
• Observability and debuggability
• Targeted assertions where appropriate
• Ability to review verification results and debug issues.
• Verification ownership is not the focus of this role.

Tools & environment

• Daily use of RTL simulators (Cadence / Synopsys / Siemens).
• Experience with lint, CDC, and basic static analysis tools.
• Comfortable in large Unix-based design environments.
• Scripting (Python / Tcl / Bash) to support design productivity.

Experience & qualifications

• ASIC / SoC digital design experience.
• Confirmed ownership of at least onemajor design block end-to-end.
• Degree in Electrical Engineering, Computer Engineering, or equivalent experience.

Nice to have

• Experience with memory controllers, high-speed IO, fabrics, or sophisticated control subsystems.
• Prior exposure to timing closure considerations.
• Familiarity with formal techniques (nice to have, not required).

In return

You’ll work ongroundbreaking SoCs, with the autonomy to shape design direction, influence architecture decisions, and see your designs impact products used across the industry.

Arm offers competitive compensation, flexible working, and a collaborative engineering culture that values technical excellence.

Equal opportunities

Arm is committed to building a diverse and inclusive workplace. We welcome applicants from all backgrounds and are happy to support reasonable adjustments throughout the hiring process.

Accommodations at Arm

At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email [e-mail]. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.

Hybrid Working at Arm

Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.

Equal Opportunities at Arm

Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.