Digital IC Design Engineer

microTECH Global Ltd; Auvergne-Rhône-Alpes; Sur place; EUR 40 000 - 70 000; Plein temps

Résumé du poste

A leading technology firm based in Grenoble is seeking a skilled Digital IC Design Engineer. The ideal candidate will have a MSc or PhD in Electrical Engineering and 3+ years of experience in RTL design and verification. Responsibilities include defining digital sub-block architectures, conducting RTL design, and collaborating with teams. Strong skills in VHDL, Verilog, and system verilog are essential. Fluency in English is required.

Qualifications

• 3+ years of hands-on experience in micro-architecture definition, RTL design and verification.
• Solid knowledge of digital hardware description languages and scripting languages.
• Experience with design and verification of digital functions for Mixed-Signal ICs is a plus.

Responsabilités

• Derive specifications and define the micro-architecture of the digital sub-blocks.
• Conduct RTL design of the digital sub-blocks (Verilog / System-Verilog).
• Elaborate detailed verification plan corresponding to circuit specifications.
• Write documentation in accordance with company QA policy.

Connaissances

Digital electronic design

Signal processing

Analytical skills

Problem-solving skills

Team player

Fluent in English

Formation

MSc or PhD in Electrical Engineering

Outils

VHDL

Verilog

System Verilog

TCL

Perl

Python

UVM methodology

Cadence

Synopsys RTL design flow

Description du poste

Overview

Position: Digital IC Design Engineer

Location: Grenoble – France

About the role :

The company’s design team is seeking a dynamic and highly motivated Digital IC design engineer who will participate to the design of a state-of-the-art CMOS Transceiver ASIC for the Communications market.

The candidate will be particularly involved in the architecture definition, design and verification of the ASIC digital sub-blocks in close collaboration with the mixed-signal and digital IC design engineers.

Responsibilities :

• Derive specifications and define the micro-architecture of the digital sub-blocks
• RTL design of the digital sub-blocks (Verilog / System-Verilog)
• Elaborate detailed verification plan corresponding to the circuit specifications
• Write SDC constraints
• Define block and top-level self-checking test benches RTL and gate level netlist
• Participate to the evaluation of the fabricated ASIC in our measurement lab
• Work in team to successfully design a state-of-the art ASIC
• Participate to design reviews
• Write documentation in accordance with company QA policy

Qualifications and Requirements :

• You have a MSc or PhD in Electrical Engineering or equivalent and 3+ years of hands-on experience in micro-architecture definition, RTL design and verification
• You have a solid background in digital electronic and signal processing
• You have solid knowledge of a digital hardware description languages (VHDL or Verilog) and scripting languages (TCL, Perl, Python)
• You have solid knowledge of System Verilog
• Experience of UVM methodology is a plus
• You demonstrate good analytical and problem-solving skills
• A previous experience in design and verification of digital functions for Mixed-Signal ICs such as A / D Converters, D / A Converters, and / or RF transceivers is a plus
• A previous experience with Cadence or Synopsys RTL design flow is a plus
• You are a team player with a critical attitude and sense of initiative
• You communicate fluently in English (oral and written)