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Senior RTL Verification Engineer (SystemVerilog, UVM)
Descripción de la vacante
A leading technology recruitment firm in Spain is seeking a Senior Functional Verification Engineer to join the Verification Team. In this role, you will ensure the correctness and functionality of complex digital designs using advanced verification methodologies and tools. The ideal candidate will have industry experience in functional verification and expertise in SystemVerilog, UVM, and various scripting languages. The company offers competitive compensation and a supportive work environment.
Servicios
Formación
- Significant industry experience in functional verification.
- Hands-on experience with simulation tools and methodologies.
- A solid understanding of formal and dynamic verification techniques.
Responsabilidades
- Develop and execute verification plans to ensure functionality and correctness.
- Utilise SystemVerilog and UVM methodologies for validation.
- Perform formal and dynamic verification to resolve design issues.
- Leverage scripting languages for automation.
- Manage version control and troubleshoot technical challenges.
Conocimientos
Educación
Herramientas
* El índice de referencia salarialse calcula en base a los salarios que ofrecen los líderes de mercado en los correspondientes sectores. Su función es guiar a los miembros Prémium a la hora de evaluar las distintas ofertas disponibles y de negociar el sueldo. El índice de referencia no es el salario indicado directamente por la empresa en particular, que podría ser muy superior o inferior.