Senior RTL Verification Engineer (SystemVerilog, UVM)

IC Resources; Madrid; Presencial; EUR 55.000 - 75.000; Jornada completa

Descripción de la vacante

A leading technology recruitment firm in Spain is seeking a Senior Functional Verification Engineer to join the Verification Team. In this role, you will ensure the correctness and functionality of complex digital designs using advanced verification methodologies and tools. The ideal candidate will have industry experience in functional verification and expertise in SystemVerilog, UVM, and various scripting languages. The company offers competitive compensation and a supportive work environment.

Servicios

Flexible work environment

Competitive compensation

Culture of continuous learning and growth

Formación

• Significant industry experience in functional verification.
• Hands-on experience with simulation tools and methodologies.
• A solid understanding of formal and dynamic verification techniques.

Responsabilidades

• Develop and execute verification plans to ensure functionality and correctness.
• Utilise SystemVerilog and UVM methodologies for validation.
• Perform formal and dynamic verification to resolve design issues.
• Leverage scripting languages for automation.
• Manage version control and troubleshoot technical challenges.

Conocimientos

SystemVerilog

UVM methodologies

Python

Perl

Bash

TCL

Version control

Educación

Master’s or PhD in a relevant field

Herramientas

Simulation tools

Regression tools

Git

SVN

Descripción del empleo

A leading technology recruitment firm in Spain is seeking a Senior Functional Verification Engineer to join the Verification Team. In this role, you will ensure the correctness and functionality of complex digital designs using advanced verification methodologies and tools. The ideal candidate will have industry experience in functional verification and expertise in SystemVerilog, UVM, and various scripting languages. The company offers competitive compensation and a supportive work environment.