ASIC DRAM circuit design

North American Production Sharing de México, S.A. de C.V.; Tijuana; Presencial; MXN 70,000 - 90,000; Jornada completa

Descripción de la vacante

A technology solutions company is seeking a highly skilled engineer to develop 2.5D/3D chiplet and networking solutions. The candidate will drive innovation through technology knowledge, interpreting use cases, and working with teams on architecture designs. Requirements include a Master's/PhD in Electrical Engineering or related fields and significant experience in heterogeneous systems. This role is crucial for influencing the next generation of SoC and platform architectures while ensuring optimal performance in AI applications.

Formación

• Master's or PhD in relevant field is mandatory.
• 5+ years of experience required for Bachelor's.
• 4+ years required for Master's degree holders.
• 3+ years required for PhD holders.

Responsabilidades

• Develop 2.5D/3D partitions for SoC and platform architectures.
• Drive innovation mapping AI use cases to integration solutions.
• Perform system KPI analysis for architecture drives.
• Work with internal teams on system and architecture.
• Apply technology knowledge to influence next-gen designs.

Conocimientos

Experience with 2.5D and 3D STCO and pathfinding

Excellent understanding of AI use case KPI dependency

Good knowledge of heterogeneous architecture

Basic programming skills

Ability to work across teams and BUs

Advanced data analysis and interpretation skills

Educación

Master's or PhD in Electrical Engineering

Bachelor’s degree in science, Engineering, or related field

Descripción del empleo

We are seeking a highly skilled engineer to develop 2.5D/3D chiplet and networking solution based on technology-systems co-optimized for a unique era of heterogeneous compute as Moore’s law slows down. The candidate is expected to be an expert in recent technology-architecture trends for heterogeneous low power high performance compute and AI compute. He/she should be able to apply that knowledge to influence the company’s next generation SoC and platform architectures, including partitions for logic and Cache, DRAM memories, and involving 2.5D/3D chiplets and networking technologies to connect them. Knowledge of emerging optical networking technology is a plus.

Candidate will also drive innovation in the group and across the company’s product BUs to effectively map emerging AI and other compute use cases to process and chip-integration solutions with detailed knowledge of process technology, 2.5D/3D chiplet architecture, networking technologies, and trade-offs. Knowledge of different IPs (e.g., CPU, GPU, NPU) and how they act together to drive an E2E use case is a plus. Candidate will work with internal architecture and system teams to develop 2.5D/3D partitions and map to 3D stacking topologies. Candidate will perform system KPI analysis to drive 3D architecture and stacking strategies for new product introduction.

Minimum Qualifications

• Experience with 2.5D and 3D STCO and pathfinding.
• Excellent understanding of generic and AI use case KPI dependency on process and system architecture involving 2.5D/3D chiplets and networking technologies.
• Good knowledge of heterogeneous architecture, 2.5D/3D integration schemes.
• Basic programming skills e.g., ability to model (e.g., in Python or other languages), system use case impact of 3D architectures, and integration schemes.
• Master's or PhD in Electrical Engineering, Computer Science, or a related field.
• Ability to work across teams and BUs.
• Ability to work without supervision and as part of a team.
• Most tasks do not have defined steps; simultaneous use of multiple mental abilities is generally required to determine the best approach.
• Advanced data analysis and interpretation skills are required.

Education

• Bachelor’s degree in science, Engineering, or related field and 5+ years of relevant heterogeneous System and technology or related work experience.
• OR master's degree in science, Engineering, or related field and 4+ years of heterogeneous System and technology or related work experience.
• OR PhD in Science, Engineering, or related field and 3+ years of heterogeneous System and technology or related work experience.