STA Expert Engineer - ASIC Timing & Sign-off (R&D)

Atos SE; Les Clayes-sous-Bois; Sur place; EUR 40 000 - 60 000; Plein temps

Résumé du poste

A leading technology company is seeking a STA expert engineer for its R&D team in the Paris area. The successful candidate will focus on timing constraints definition and analysis for integrated circuits. With a minimum of 5 years of experience in timing analysis tools, you'll work closely with design and flow teams to ensure timing closure for ASIC flows. This role requires a strong engineering background, expertise in TCL, and fluent English. Competitive compensation and opportunities for growth are offered.

Qualifications

• Bac + 5 in micro‑electronics and/or integrated circuits.
• 5+ years of experience in timing constraints generation.
• Fluent in English for collaboration.

Responsabilités

• Generate timing constraints for ASIC flow.
• Set timing analysis tool settings for sign‑off.
• Perform STA Sign‑off at top level.

Connaissances

Timing constraints generation

Timing analysis tools (Synopsys, Cadence)

TCL programming

Perl and/or Python programming

Clock Domain Crossing (CDC) timing issues

Formation

Engineering degree or equivalent (Bac + 5)

Outils

Git

Description du poste

A leading technology company is seeking a STA expert engineer for its R&D team in the Paris area. The successful candidate will focus on timing constraints definition and analysis for integrated circuits. With a minimum of 5 years of experience in timing analysis tools, you'll work closely with design and flow teams to ensure timing closure for ASIC flows. This role requires a strong engineering background, expertise in TCL, and fluent English. Competitive compensation and opportunities for growth are offered.