Lead AE in Digital and STA

Cadence Design Systems; Meylan; Sur place; EUR 45 000 - 65 000; Plein temps

Résumé du poste

A leading software company is looking for an Application Engineer in Timing Analysis based in Grenoble. The role involves working on SoC projects and ensuring the performance of timing analysis tools through testing and optimization. Candidates should have 4 to 10 years of experience in digital design and knowledge of STA methodologies. Proficiency in scripting and familiarity with Cadence tools are advantageous. Fluency in English is required, and knowledge of French is a plus.

Qualifications

• 4 to 10 years of experience in digital design flow and timing analysis.
• Hands-on experience with timing optimization, SDC and CDC checks.
• Good understanding of digital IC design and EDA tools.

Responsabilités

• Validate new tool releases through exhaustive regression testing.
• Understand and enhance timing analysis mechanisms for advanced nodes.
• Investigate and resolve complex timing issues.

Connaissances

Static Timing Analysis (STA)

Digital implementation flows

Scripting (C-shell, TCL/TK, Python)

Timing optimization

Communication skills

AI/ML techniques

Fluent in English

Fluent in French

Formation

Degree in Electrical/Electronic Engineering

Outils

Cadence Innovus

Cadence Tempus

UNIX/Linux

Description du poste

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are looking for an Application Engineer in Timing Analysis, located in Grenoble

Job Description, Role and Key Responsibilities

This is an excellent opportunity to work on challenging and complex SoC projects at advanced technology nodes with leading companies in the semiconductor domain.

• Validate new tool releases through exhaustive regression testing in collaboration with Product Engineers & Product Validation Engineers. Enhance current processes to run regression tests, validate results and coordinate kit/tool versions.
• Understand and enhance timing analysis mechanisms for advanced nodes.
• Investigate and resolve complex timing issues, including algorithmic and physical phenomena.
• Learn and analyse dependencies between timing analysis and the broader digital implementation flow.
• Write and maintain timing constraints; perform cross-domain clock checking as part of signoff validation.
• Assist in integrating new STA requirements into the tool for advanced technologies.
• Promote and present new features; guide and support customers in integrating the latest Tempus technologies into their design flow.
• Support customers in using signoff tools on live projects, including:
  • Timing optimization setup issues and convergence challenges in our digital tool suite
  • Support timing ECO flows and globally contribute to improving workflows and tool efficiency

Requirement, Experience, Education

• Good knowledge of Static Timing Analysis (STA) and signoff methodologies.
• Hands‑on experience with digital implementation flows, timing optimization, SDC and CDC checks.
• A working knowledge of UNIX/Linux, scripting (C-shell, TCL/TK, Python).
• Exposure to AI/ML techniques and interest in applying them for design optimization, verification, or predictive analysis.
• Good understanding of digital IC design and EDA tools (experience with Cadence Innovus/Tempus is a plus).

• Around 4 to 10 years of experience in digital design flow and timing analysis

• Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline.
• Good communication skills; fluent in English and French is a plus

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